Abstract: The present disclosure relates to an apparatus for adjusting AC-DC converter output voltage, the apparatus includes a plurality of ports, an AC-DC converter circuit, a plurality of DC-DC converters coupled to a plurality of controllers, where the plurality of controllers coupled to corresponding plurality of ports to operate the one or more loads, wherein at least one controller is a master controller and the other plurality of controllers are slave controllers. The master controller configured to determine, from the slave controllers power levels for each port, calculate an optimal input voltage value for the DC-DC converters and communicate the calculated value to the AC-DC converter circuit through a constant current source to regulate the amount of DC voltage that is being supplied to the DC-DC converters to operate the one or more loads, thereby leading to improved system efficiency of multiport USB based power adapter.

Abstract: The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.

Abstract: Systems and methods for detecting electrical connection and disconnection on an USB Type-A charging port like power adapters, power banks and car chargers having one or more USB Type-A charging port of an USB device. The system includes: a voltage source; a MOSFET SWITCH gate driver, in USB type-A connected state, that operatively couples MOSFET SWITCH with voltage source and VBUS supply of USB type-A port; charge pump; a current sense differential amplifier; and a control unit configured to: monitor VBUS current, and detect potential disconnected state of connected USB type-A port; and monitor VBUS voltage and compare VBUS voltage with predetermined voltage to sense external condition such that VBUS voltage drops because of load capacitance and load current. The control unit is further configured to, when the duty cycle has reached a minimum VBUS current, detect the USB type-A disconnection with a charge pump state.

Abstract: A multiport universal serial bus (USB)-C based power supply device including a USB type-C port configured to supply power to a connected type-C external device, at least one USB type-A port configured to supply power to at least one connected type-A external sink device, a configurable power source and a controller operatively coupled with the configurable power source, the USB type-C port and at least one of the USB type-A port. The controller is configured to generate, based on the generated type-C and type-A power profile, at least one of a digital communication signal and a feedback control signal, which correspond to a power value to be supplied, based on the generated power profile, to the type-C port and the at least one type-A port respectively. Operation of the multiport USB-C based power supply device by a single controller facilitates compact construction of the multiport USB-C based power supply device.

Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.

Abstract: The present disclosure provides a bidirectional hybrid power converter that may include an input circuit consisting of an input power supply and input capacitor, a plurality of switches connected to each other, to input power supply to a set of passive electronic components, to ground and to an output circuit comprising one or more output terminals, each consisting of an output capacitance. The plurality of switches is connected directly or through passive electronic components in an arrangement to obtain a plurality of power converter networks for battery charging as well as other applications by reuse of a set of plurality of switches. The input power supply and the output load are referred to based on the direction of the power conversion flow, forward or reverse. The first terminal can be connected to both a power source as an input and load as an output.

Abstract: Systems and methods for detecting electrical connection and disconnection on an USB Type-A charging port like power adapters, power banks and car chargers having one or more USB Type-A charging port of an USB device. The system includes: a voltage source; a MOSFET SWITCH gate driver, in USB type-A connected state, that operatively couples MOSFET SWITCH with voltage source and VBUS supply of USB type-A port; charge pump; a current sense differential amplifier; and a control unit configured to: monitor VBUS current, and detect potential disconnected state of connected USB type-A port; and monitor VBUS voltage and compare VBUS voltage with predetermined voltage to sense external condition such that VBUS voltage drops because of load capacitance and load current. The control unit is further configured to, when the duty cycle has reached a minimum VBUS current, detect the USB type-A disconnection with a charge pump state.

Abstract: System and method for fault identification and fault handling in MPSD are provided. The system includes: a multi-port power sourcing device including multiple ports, a master is configured to: send a slave discovery request to multiple slave ports, receive a slave discovery response from the multiple slave ports; reset the watchdog timer in the multiple ports by sending watchdog refresh instruction periodically; each of the multiple ports experience watchdog timer timeout upon failing to receive the watchdog refresh instruction, generate their corresponding port reset upon watchdog timer timeout, to resolve one or more faults associated with the corresponding port; the multiple ports include a role change staggered timer which is triggered upon the corresponding watchdog timer timeout, and reset upon receiving the watchdog refresh instruction from master; the slave ports for which role change staggered timer times out first, changes the role to start functioning as the new master port.

Abstract: The present disclosure provides an apparatus and a method for implementing a USB-IF certified programmable power supply algorithm on a USB-C port. The method involves using a software code running on a microcontroller which monitors voltage and current being supplied by a power supply controller IC on a VBUS line of the USB-C port. Based on the detected voltage/current corrective actions are taken by the software code to bring the voltage/current to accepted levels as requested by a port partner. Further, a PPS accelerator is configured to compute an average or a new current/voltage value and provide the computed average or a new current/voltage value to a microcontroller for subsequent decision making and for other related assessment process.

Abstract: The present disclosure relates to a method and system to facilitate temperature-aware redistribution of power in a power sourcing device comprising plurality of ports. The method can include monitoring, by using one or more sensors coupled to the power sourcing device, a first temperature associated with a first port of the plurality of ports to obtain a first set of signals and executing, at the power sourcing device, based on a second set of signals obtained from the first set of signals, a first set of instructions associated with redistribution of power from the first port to second port of the plurality of ports, wherein the second set of signals can indicate exceeding of the first temperature above the predefined threshold temperature value.

Abstract: The present disclosure relates to a system for real-time debugging of microcontroller, the system includes a microcontroller configured in an embedded device to execute a set of instructions, the microcontroller includes a counter unit that generates a set of values for the executed set of instructions. An on-chip debugger (OCD) fetches a selective set of data packets of the set of instructions from the microcontroller. An encoder encodes the selective set of data packets to store the encoded set of data packets in a storage unit, wherein encoding of the set of data packets is performed to compress the data for minimal information size such that the external debugger unit (EDU) receives the encoded set of data packets with minimal information size through the external interface.

Abstract: The present disclosure provides a system and method for soft start scheme to control inrush current for VCONN in USB-C interface. The system includes: a serial shift register having flip-flops and adapted to obtain clock with programmable clock divider, frequency of clock changes dynamically by programming programmable clock divider; a resistor DAC unit configured to increment voltage in step-wise manner; a pass gate switch comprising NMOS gate switch and a PMOS gate switch connected in parallel and operatively coupled to the resistor DAC unit and configured to control an input voltage to a VCONN charge pump, said input voltage being in incremental steps such that the VCONN charge pump pumps an output voltage; and a VCONN switch gate operatively coupled to the VCONN charge pump and configured to supply the output voltage in controlled, incremental steps, such that the output voltage is ramped slowly to control the inrush current.

Abstract: The present disclosure provides a transceiver for transmission of data coded according to a Bi-phase Mark Coding (BMC) protocol through a configurable channel (CC) of a USB type-C port. The transceiver includes: a transmitter configured to receive the coded BMC data and transmit the coded BMC data through the CC line. The transmitter includes: a low dropout (LDO) regulator configured to receive a reference voltage (VREF) and generate a local programmable supply voltage; a delay control logic configured to receive the BMC data, and including flipflops connected in series, wherein, output from each flipflop is delayed with respect to input received by the flipflop; and a transmitter driver configured to receive output from each flipflop of the delay control logic, the transmitter driver including a NMOS switches and a PMOS switches. The transceiver includes an eye correction receiver configured to receive output from the transmitter driver of the transmitter.

Abstract: Systems and methods for providing VCONN to configuration channel line in USB-interface, involving a sense switch and a VCONN switch coupled with the VCONN supply and a gate control unit; an over current protection (OCP) reference current unit configured to provide a predetermined current through the sense branch; a preamplifier configured to amplify a differential voltage between source terminal voltages of the sense switch and the VCONN switch; an Over Current detection comparator configured to generate an Over Current fault signal when the source terminal voltage at the VCONN switch is lower than the source terminal voltage at the sense switch; and a control unit configured to: activate, upon receipt of the generated Over Current fault signal, the gate control unit, wherein the gate control unit, upon activation, is configured to disable the sense switch and the VCONN switch respectively to protect the VCONN and CC_P from over current.

Abstract: A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.

Abstract: Systems involve a dividing unit configured to divide functionality in digital hardware portion through finite state machines (FSMs), protocol timers and PD message accelerator blocks for reducing code size such that their implementation combined with a low code-size firmware (FW) interacts, using a control unit operatively coupled to the dividing unit, with the hardware portion to provide updates in an USB-PD specification, wherein at least one of the FSMs configured to run at a predefined UI clock frequency to enable low active power to the system, a wake-up unit running at least on 4 times of UI clock frequency and detects data edge on configuration channel line to wake-up the entire system from sleep state, wherein a plurality of standard power saving mechanisms selected from clock gating and frequency reduction for clocks are implemented to enable low power corresponding to the system and bypass paths at each level of implementation.

Abstract: The present disclosure provides an analogue to digital converter (ADC) (100), which includes: a capacitive digital to analogue converter (DAC) (120) configured to sample and hold a received sampling input signal and a latched comparator (140) including a first metal oxide semiconductor field effect transistor (MOSFET) (202); a second MOSFET (204) connected in parallel to the first MOSFET; a third MOSFET (226), wherein a third source terminal of the third MOSFET (226) is coupled with first drain terminal and second drain terminal of the first and second MOSFET (202, 204), wherein a sampling switch (130) is configured to the third source terminal to selectively allow voltage to be supplied to the third MOSFET (226), and wherein the sampling switch is configured to disallow voltage to be supplied to the third MOSFET when the ADC is sampling the input signal.

Abstract: The present disclosure provides a system and method including: a first USB port and one or more second USB ports provided on the multi-port adapter; an AC-DC conversion configured to measure a first load current at the first USB port; a plurality of buck-boost mode power conversion units, each configured to measure a second load current at a corresponding one or more second USB ports; and a system controller configured to measure the first load current and the one or more second load currents, wherein the system controller is configured to compare and adjust the measured first load current and the measured one or more second load currents to, respectively, a first rated current and a corresponding second rated current for each of the one or more second USB ports.

Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.

Abstract: An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.