Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N-type dopant is implanted through the bottom of the trench into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract: This invention relates to driving solenoid and motor loads while providing the means for fast turn on and fast turn off. Many applications including automotive fuel injector drivers, Anti-Skid Braking (ABS) solenoid and motor drivers, and other electro-mechanical motion control require the ability to quickly turn on or off a number of devices. The invention utilizes a bridge architecture to drive the loads and to turn on and off individual devices. The invention employs a diode and a switch for each device controlled plus a single master diode and a single master switch. The invention thereby reduces the number of components needed to control N devices to 2*N+2 from prior art half bridge circuit 4*N. Novel techniques and algorithms are used to multiplex the single master switch and control multiple inductive devices. The system provides redundant control and error checking means to preclude single point failure mechanisms.

Abstract: A voltage converter has a control circuit that generates a PWM voltage from a DC input voltage, a housekeeping coil and a first voltage rectifier-filter which supply power to the control circuit from an induced voltage in the housekeeping coil, and a second voltage rectifier coupled to the housekeeping coil to rectify flyback (or reset) voltages in the housekeeping coil. The rectified flyback voltage controls the frequency of the PWM voltage generated by the control circuit. During an overload, the control circuit reduces the duty cycle of the PWM voltage. In response, the magnitude of the rectified flyback voltage falls which causes the frequency of the PWM voltage to be reduced. The first and second voltage rectifiers may be coupled to different taps of the housekeeping coil, so that both voltage rectifiers provide positive voltages relative to a ground tap even though the two voltage rectifiers rectify pulses of opposite polarity on the secondary coil.

Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.

Abstract: A process is taught which provides very shallow conductive regions in a semiconductor material by the formation of a fixed charge placed in an overlying dielectric layer which induces an inversion region in the underlying semiconductor. The inversion region so formed is used as a MOSFET drain extension between a drain contact region and the channel located beneath the gate region. The conductivity of the induced inversion region is controlled by the concentration of the ionic charge present in the dielectric layer.

Abstract: A V-groove metal oxide semiconductor field effect transistor (V-MOSFET) including a body of semiconductor material having three plane regions defining two plane rectifying junctions. A V-groove extends into said body through said two junctions from one surface. The plane region at said surface comprises the source, the intermediate plane region, the channel, and the other region, the drain. A gate electrode is formed over an insulating layer in said groove, a source electrode connects to said source and channel regions and a drain electrode is connected to said drain region. A moat surrounds said transistor and penetrates the source and channel regions and a field electrode is disposed over an insulating layer covering the moat wall.

Abstract: CMOS device and method utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.

Abstract: Analog to digital converter of the type in which an analog input signal is integrated and charge is applied to the integrating capacitor in predetermined measured quantities to offset or balance the effect of the input signal. A counter is incremented and decremented in accordance with the balancing charge to provide a count corresponding to the input signal. Means is included for eliminating errors due to offset voltages and imperfections in the virtual ground of the integrator, and the operating level of the integrator during a conversion is set independently of the sources which supply the balancing charge.