Abstract: A chip carrier for testing electrical performance of a passive component includes: a core layer having a plurality of conductive traces on a surface thereof; at least one first trace connected with the passive component and having a first predetermined position and two ends, wherein the two ends are respectively electrically connected to a first bond finger on the surface of the chip carrier and to a first ball pad on an opposite surface of the chip carrier; at least one second trace not connected with the passive component and having two ends and a second predetermined position located on the same surface as the first predetermined position, one end of the second trace being electrically connected to a second ball pad located on the same surface as the first ball pad; and a solder mask layer applied over the conductive traces, with the first and second predetermined positions exposed.

Abstract: The present invention provides schemes which are associated with wire bonding process or wire bonding machine to detect the bonding status of a bonding wire of a package including at least a semiconductor unit. The schemes are very useful to a BGA (Ball Grid Array) package or similar types of packages, and provide significant advantages particularly for a package in which the resistance (such as the resistance resulting from an adhesion layer and a layer of Cupric Oxide for promoting adhesion) between a semiconductor unit and its carrier is not low enough.

Abstract: The present invention provides schemes which are associated with wire bonding process or wire bonding machine to detect the bonding status of a bonding wire of a package including at least a semiconductor unit. The schemes are very useful to a BGA (Ball Grid Array) package or similar types of packages, and provide significant advantages particularly for a package in which the resistance (such as the resistance resulting from an adhesion layer and a layer of Cupric Oxide for promoting adhesion) between a semiconductor unit and its carrier is not low enough.

Abstract: A semiconductor package with a heat-dissipating structure and method for making the same are proposed. The heat-dissipating structure includes a heat sink and a plurality of solder columns, wherein the solder columns are attached at ends thereof to the heat sink and to a substrate, so as to support the heat sink to be positioned above a semiconductor chip mounted on the substrate. A re-flow process performed after the attachment of the heat-dissipating structure to the substrate allows the self-alignment of the solder columns with respect to predetermined positions on the substrate, which helps precisely control the positioning of the heat-dissipating structure on the substrate fixed thereon. Moreover, the use of the solder columns is able to protect the substrate from being damaged or deformed during molding process. In addition, the heat-dissipating structure is simple in structure, which simplifies the manufacturing process and reduces the cost.

Abstract: A layout method is proposed for semiconductor package substrate with plating bus, such as TFBGA (Thin & Fine Ball Grid Array) substrate, which can help allow each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. The proposed layout method is characterized in the provision of a plating bus of a special layout pattern for interconnecting all the via lands alongside each singulation line. The plating bus includes a plurality of crosswise segments, each being used to to interconnect one crosswise-opposite pair of the via lands across the singulation line; and a plurality of diagonal segments, each being used to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line. The proposed layout method allows each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process.

Abstract: A heat-dissipating device is designed for use in an integrated circuit package for heat dissipation. The heat-dissipating device is a molded piece of a heat-conductive material, having an exterior side which is to be exposed to the outside of the integrated circuit package. The heat-dissipating device is characterized in the forming of a staircase-like cutaway part at the edge of the exterior side thereof, which is formed with a plurality of stepped surfaces. During the molding process, the staircase-like cutaway part can help slow down the flowing speed of the encapsulation resin flow, so that the resin flow would hardly flash onto the exterior side of the heat-conductive device. In addition, the staircase-like form of the cutaway part provides a lengthier path that would hardly allow outside moisture to penetrate to the inside of the integrated circuit package and cause popcorn effect in the integrated circuit package. The manufactured integrated circuit package is therefore more reliable to use.