Abstract: The present invention pertains to a clock generator that provides a plurality of dock outputs, each of which can be synchronized from one of several possible sets of references. Multiple frequency synthesizers are used to generate the clocks at the desired frequencies. These frequency synthesizers operate on the principle of dividing a supplied reference dock by an integer (I), plus a ratio (R/M), whereby there are approximately I plus (R/M) input clock cycles per output clock cycle. The output of a frequency synthesizer is a train of pulses with its duration equal to the period of the reference clock and at a rate equal to N/D=1/(I+R/M) times the reference clock rate. In order to generate an output signal with a more uniform duty cycle, the pulse train drives a toggle select circuit. The function of the toggle select circuit is to remove half of the phase quantization due to the limited frequency resolution of the reference dock.