Patents Assigned to SILMINDS, LLC, EGYPT
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Patent number: 8812575Abstract: A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the eType: GrantFiled: July 6, 2011Date of Patent: August 19, 2014Assignee: SilMinds, LLC, EgyptInventors: Ramy Raafat, Amira Mohamed, Hossam Ali Hassan Fahmy, Yasmeen Farouk, Mostafa Elkhouly, Tarek Eldeeb, Rodina Samy
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Patent number: 8805917Abstract: A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.Type: GrantFiled: July 6, 2011Date of Patent: August 12, 2014Assignee: SilMinds, LLC, EgyptInventors: Amira Mohamed, Ramy Raafat, Hossam Ali Hassan Fahmy, Tarek Eldeeb, Yasmeen Farouk, Rodina Samy, Mostafa Elkhouly
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Patent number: 8788560Abstract: A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.Type: GrantFiled: November 9, 2011Date of Patent: July 22, 2014Assignee: SilMinds, LLC, EgyptInventors: Tarek Eldeeb, Hossam Aly Hassan Fahmy, Mahmoud Y. Hassan
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Patent number: 8751555Abstract: A method for performing a decimal floating-point division, including: receiving, by a decimal floating-point divider, a decimal floating-point dividend and a decimal floating-point divisor; obtaining, by the decimal floating-point divider, a preliminary quotient having a first precision level, where the preliminary quotient is calculated from the decimal floating-point dividend and the decimal-floating point divisor; receiving, by the decimal floating-point divider, a rounding mode; selecting a rounding action based on the preliminary quotient and the rounding mode; and obtaining a rounded quotient having a second precision level by rounding the preliminary quotient according to the rounding action, where the first precision level is at least one digit greater than the second precision level.Type: GrantFiled: July 6, 2011Date of Patent: June 10, 2014Assignee: SilMinds, LLC, EgyptInventors: Amira Mohamed, Hossam Ali Hassan Fahmy, Ramy Raafat, Yasmeen Farouk, Mostafa Elkhouly, Rodina Samy, Tarek Eldeeb
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Publication number: 20140101215Abstract: A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors.Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Applicant: SILMINDS, LLC, EGYPTInventors: Ahmed A. Ayoub, Hossam Aly Hassan Fahmy, Tarek Eldeeb
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Patent number: 8694572Abstract: A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.Type: GrantFiled: July 6, 2011Date of Patent: April 8, 2014Assignee: SilMinds, LLC, EgyptInventors: Rodina Samy, Hossam Ali Hassan Fahmy, Tarek Eldeeb, Ramy Raafat, Yasmeen Farouk, Mostafa Elkhouly, Amira Mohamed
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Publication number: 20130117341Abstract: A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.Type: ApplicationFiled: November 9, 2011Publication date: May 9, 2013Applicant: SILMINDS, LLC, EGYPTInventors: Tarek Eldeeb, Hossam Aly Hassan Fahmy, Mahmoud Y. Hassan
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Publication number: 20120011182Abstract: A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the eType: ApplicationFiled: July 6, 2011Publication date: January 12, 2012Applicant: SILMINDS, LLC, EGYPTInventors: Ramy Raafat, Amira Mohamed, Hossam Ali Hassan Fahmy, Yasmeen Farouk, Mostafa Elkhouly, Tarek Eldeeb, Rodina Samy
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Publication number: 20120011187Abstract: A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.Type: ApplicationFiled: July 6, 2011Publication date: January 12, 2012Applicant: SILMINDS, LLC, EGYPTInventors: Amira Mohamed, Ramy Raafat, Hossam Ali Hassan Fahmy, Tarek Eldeeb, Yasmeen Farouk, Rodina Samy, Mostafa Elkhouly
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Publication number: 20120011181Abstract: A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.Type: ApplicationFiled: July 6, 2011Publication date: January 12, 2012Applicant: SILMINDS, LLC, EGYPTInventors: Rodina Samy, Hossam Ali Hassan Fahmy, Tarek Eldeeb, Ramy Raafat, Yasmeen Farouk, Mostafa Elkhouly, Amira Mohamed