Patents Assigned to Siltron Inc.
  • Patent number: 8821219
    Abstract: A wafer unloading system and wafer processing equipment (system) including the same are disclosed. The wafer unloading system includes a fluid supply tube for supplying a fluid, a nozzle for injecting the supplied fluid, and an injection hole defined in a plate to allow the injected fluid to reach a space between a polishing pad and a wafer.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: September 2, 2014
    Assignee: Siltron Inc.
    Inventors: Jin-Woo Ahn, Eun-Suck Choi, Bong-Woo Kim, Hwan-Su Yu, Jae-Hwan Yi
  • Patent number: 8557619
    Abstract: A method of manufacturing LED display is provided. The method provides a sacrificial substrate on which RGB LED device layers are formed, respectively. The method etches and patterns the LED device layer to manufacture RGB LED devices, respectively. The method removes the sacrificial substrate in a lower side of the LED device. The method contacts a stamping processor to the RGB LED devices to separate the RGB LED devices from the sacrificial substrate. The method transfers the LED device, which is attached to the stamping processor, to a receiving substrate.
    Type: Grant
    Filed: August 7, 2010
    Date of Patent: October 15, 2013
    Assignee: Siltron Inc.
    Inventors: Keon Jae Lee, Sang Yong Lee, Seung Jun Kim
  • Patent number: 8349075
    Abstract: The present invention reports a defect that has not been reported, and discloses a defect-controlled silicon ingot, a defect-controlled wafer, and a process and apparatus for manufacturing the same. The new defect is a crystal defect generated when a screw dislocation caused by a HMCZ (Horizontal Magnetic Czochralski) method applying a strong horizontal magnetic field develops into a jogged screw dislocation and propagates to form a cross slip during thermal process wherein a crystal is cooled. The present invention changes the shape and structure of an upper heat shield structure arranged between a heater and an ingot above a silicon melt, and controls initial conditions or operation conditions of a silicon single crystalline ingot growth process to reduce a screw dislocation caused by a strong horizontal magnetic field and prevent the screw dislocation from propagating into a cross slip.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: January 8, 2013
    Assignee: Siltron Inc.
    Inventors: Do-Won Song, Young-Hun Kim, Eun-Sang Ji, Young-Kyu Choi, Hwa-Jin Jo
  • Patent number: 8298926
    Abstract: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: October 30, 2012
    Assignees: Siltron Inc., Hynix Semiconductor Inc.
    Inventors: Hyung-Kook Park, Jin-Kyun Hong, Kun Kim, Chung-Geun Koh
  • Publication number: 20120233930
    Abstract: The present invention relates to a grinding wheel truing tool, its manufacturing method, and a truing apparatus, a method for manufacturing a grinding wheel and a wafer edge grinding apparatus using the same. The grinding wheel truing tool of the present invention compensates a groove of a fine-grinding wheel for fine-grinding a wafer edge, and includes a truer having an edge of the same angle as a slanted surface of the groove of the fine-grinding wheel and a cross-sectional shape corresponding to a cross-sectional shape of the groove. The present invention uses the truing tool to easily process the groove of the grinding wheel for fine-grinding the wafer edge.
    Type: Application
    Filed: April 9, 2012
    Publication date: September 20, 2012
    Applicant: SILTRON INC.
    Inventors: Yong-Dug KIM, Gye-Je CHO, Mun-Suk YONG, Hwan-Yun JUNG, Kyung-Moo LEE, Dong-Hwan HYUN, Jae-Young KIM
  • Patent number: 8216372
    Abstract: The invention relates to an apparatus and method for growing a high quality Si single crystal ingot and a Si single crystal ingot and wafer produced thereby. The growth apparatus controls the oxygen concentration of the Si single crystal ingot to various values thereby producing the Si single crystal ingot with high productivity and extremely controlled growth defects.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: July 10, 2012
    Assignee: Siltron Inc.
    Inventor: Hyon-Jong Cho
  • Publication number: 20120141808
    Abstract: The present invention reports a defect that has not been reported, and discloses a defect-controlled silicon ingot, a defect-controlled wafer, and a process and apparatus for manufacturing the same. The new defect is a crystal defect generated when a screw dislocation caused by a HMCZ (Horizontal Magnetic Czochralski) method applying a strong horizontal magnetic field develops into a jogged screw dislocation and propagates to form a cross slip during thermal process wherein a crystal is cooled. The present invention changes the shape and structure of an upper heat shield structure arranged between a heater and an ingot above a silicon melt, and controls initial conditions or operation conditions of a silicon single crystalline ingot growth process to reduce a screw dislocation caused by a strong horizontal magnetic field and prevent the screw dislocation from propagating into a cross slip.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 7, 2012
    Applicant: SILTRON INC.
    Inventors: Do-Won Song, Young-Hun Kim, Eun-Sang Ji, Young-Kyu Choi, Hwa-Jin Jo
  • Publication number: 20120132131
    Abstract: The present invention reports a defect that has not been reported, and discloses a defect-controlled silicon ingot, a defect-controlled wafer, and a process and apparatus for manufacturing the same. The new defect is a crystal defect generated when a screw dislocation caused by a HMCZ (Horizontal Magnetic Czochralski) method applying a strong horizontal magnetic field develops into a jogged screw dislocation and propagates to form a cross slip during thermal process wherein a crystal is cooled. The present invention changes the shape and structure of an upper heat shield structure arranged between a heater and an ingot above a silicon melt, and controls initial conditions or operation conditions of a silicon single crystalline ingot growth process to reduce a screw dislocation caused by a strong horizontal magnetic field and prevent the screw dislocation from propagating into a cross slip.
    Type: Application
    Filed: December 16, 2011
    Publication date: May 31, 2012
    Applicant: SILTRON INC.
    Inventors: Do-Won Song, Young-Hun Kim, Eun-Sang Ji, Young-Kyu Choi, Hwa-Jin Jo
  • Patent number: 8158496
    Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: April 17, 2012
    Assignee: Siltron Inc.
    Inventors: Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee, Doo-Soo Kim, Ji-Hoon Kim
  • Publication number: 20110143525
    Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.
    Type: Application
    Filed: February 21, 2011
    Publication date: June 16, 2011
    Applicant: SILTRON INC.
    Inventors: Doo-Soo Kim, Ho-Jun Lee, Yong-Jin Kim, Dong-Kun Lee
  • Patent number: 7906408
    Abstract: Provided is a method of manufacturing a strained silicon-on-insulator (SSOI) substrate that can manufacture an SSOI substrate by separating a bonded substrate using a low temperature heat treatment. The manufacturing method includes: providing a substrate; growing silicon germanium (SiGe) on the substrate to thereby form a SiGe layer; growing silicon (Si) with a lattice constant less than a lattice constant of SiGe on the SiGe layer to thereby form a transformed Si layer; and implanting ions on the surface of the transformed Si layer, wherein, while growing of the SiGe layer, the SiGe layer is doped with impurity at a depth the ions are to be implanted. Accordingly, it is possible to manufacture a substrate with an excellent surface micro-roughness. Since a bonded substrate can be separated using low temperature heat treatment by interaction between implanted ions and impurity, it is possible to reduce manufacturing costs and facilitate an apparatus.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 15, 2011
    Assignee: Siltron Inc.
    Inventors: In Kyum Kim, Suk June Kang, Hyung Sang Yuk
  • Patent number: 7901132
    Abstract: Provided is a method of identifying crystal defect regions of monocrystalline silicon using metal contamination and heat treatment. In the method, a sample in the shape of a silicon wafer or a slice of monocrystalline silicon ingot is prepared. At least one side of the sample is contaminated with metal at a contamination concentration of about 1×1014 to 5×1016 atoms/cm2. The contaminated sample is heat-treated. The contaminated side or the opposite side of the heat-treated sample is observed to identify a crystal defect region. The crystal defect region can be analyzed accurately, easily and quickly without the use of an additional check device, without depending on the concentration of oxygen in the monocrystalline silicon.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: March 8, 2011
    Assignee: Siltron Inc.
    Inventors: Sang-Wook Wee, Seung-Wook Lee, Ki-Man Bae, Kwang-Salk Kim
  • Publication number: 20110045748
    Abstract: A double side polishing apparatus comprises an upper polishing plate and a lower polishing plate for polishing both sides of a wafer; a plurality of carriers, each including a center plate and a circumferential plate, the center plate having a mounting hole where the wafer is mounted, the circumferential plate having a fitting hole where the center plate is fitted and a gear part formed along the outer periphery thereof, the center of the mounting hole being eccentric from the center of the center plate, the center of the fitting hole being eccentric from the center of the circumferential plate; and a sun gear and an internal gear engaged with the gear part to transmit a rotational force to the plurality of carriers, wherein a fitting direction of a center plate into a fitting hole is adjustable for at least two carriers among the plurality of carriers.
    Type: Application
    Filed: February 4, 2010
    Publication date: February 24, 2011
    Applicant: SILTRON INC.
    Inventors: Chi-Bok Lee, Heui-Don Cho
  • Publication number: 20100330784
    Abstract: Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process.
    Type: Application
    Filed: September 9, 2010
    Publication date: December 30, 2010
    Applicant: SILTRON INC.
    Inventors: Ho-Jun LEE, Yong-Jin KIM, Dong-Kun LEE, Doo-Soo KIM, Ji-Hoon KIM
  • Publication number: 20100158781
    Abstract: The invention relates to a technique for producing a high quality Si single crystal ingot with a high productivity by the Czochralski method. The technique of the invention can control the magnetic field strength of an oxygen dissolution region different from that of a solid-liquid interface region in order to control the oxygen concentration at a desired value.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 24, 2010
    Applicant: SILTRON INC.
    Inventor: Hyon-Jong Cho
  • Patent number: 7732352
    Abstract: By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 8, 2010
    Assignees: Hynix Semiconductor Inc., Siltron Inc.
    Inventors: Young Hee Mun, Kun Kim, Chung Geun Koh, Seung Ho Pyi
  • Patent number: 7723217
    Abstract: The present invention relates to a method for manufacturing a gallium nitride single crystalline substrate, including (a) growing a gallium nitride film on a flat base substrate made of a material having a smaller coefficient of thermal expansion than gallium nitride and cooling the gallium nitride film to bend convex upwards the base substrate and the gallium nitride film and create cracks in the gallium nitride film; (b) growing a gallium nitride single crystalline layer on the crack-created gallium nitride film located on the convex upward base substrate; and (c) cooling a resultant product having the grown gallium nitride single crystalline layer to make the convex upward resultant product flat or bend convex downwards the convex upward resultant product and at the same time to self-split the base substrate and the gallium nitride single crystalline layer from each other at the crack-created gallium nitride film interposed therebetween.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: May 25, 2010
    Assignee: Siltron Inc.
    Inventors: Ho-Jun Lee, Doo-Soo Kim, Dong-Kun Lee, Yong-Jin Kim
  • Patent number: 7708832
    Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: May 4, 2010
    Assignee: Siltron Inc.
    Inventors: Yong-Jin Kim, Ji-Hoon Kim, Dong-Kun Lee, Doo-Soo Kim, Ho-Jun Lee
  • Publication number: 20100038755
    Abstract: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.
    Type: Application
    Filed: December 27, 2007
    Publication date: February 18, 2010
    Applicants: SILTRON INC., HYNIX SEMICONDUCTOR INC.
    Inventors: Hyung Kook Park, Jin-Kyun Hong, Kun Kim, Chung-Geun Koh
  • Patent number: 7615470
    Abstract: The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: November 10, 2009
    Assignee: Siltron Inc.
    Inventors: Yong Jin Kim, Dong Kun Lee