Abstract: An electronic design automation (EDA) tool and system for physical verification of workflow for semiconductor circuit designs, and methods of using the same is described. Generally, the method includes (i) automatic splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores; (ii) extracting parasitic capacitance structures from the IC layout; (iii) generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed; and (iv) extraction of parasitic resistance structures from IC layout. In some embodiments, the IC layout is additionally or alternatively split into groups of rules for processing. Other embodiments are also described.

Abstract: An electronic design automation tool and method of operating the same are provided for placement and routing of intra-cell devices in integrated circuits (ICs). Generally the method includes: receiving inputs, creating an instance of a Satisfiability Modulo Theory (SMT) problem for placement and routing by translating the inputs into a set of SMT constraints relating to the placement of intra-cell transistors and routing for interconnects to intra-cell transistors, calling a SMT solver and using the set of SMT constraints generating a solution to the SMT problem, and if the solution satisfies requirements of the inputs and a predetermined area requirement specified by a user, creating and outputting a layout for placement and routing of intra-cell transistors in the IC. The process may be repeated until a predetermined number of ranked solutions or an optimal solution is found. Other embodiments are also disclosed.

Abstract: A physics/chemistry-based artificial intelligence driven modeling tool and method of using the same are provided for optimizing fabrication processes for microelectronic devices. Generally the method begins with assembling a training dataset including features of a target device and performance parameters of the process flow from test machine and/or simulation results. The features of the device are narrowed to a number of input features, and the device digitally modeled using a neural network and AI algorithm, based on the input features and performance parameters. The model is analyzed to find an optimal condition for at least one of the input features. A second number of input features for the device are selected based on the optimal condition(s) are found and the modeling and optimizing are repeated using a design of experiment (DoE) advanced algorithm until a digital twin model of the target device is generated.

Abstract: An electronic design automation (EDA) tool and system for physical verification of workflow for semiconductor circuit designs, and methods of using the same is described. Generally, the method includes (i) automatic splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores; (ii) extracting parasitic capacitance structures from the IC layout; (iii) generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed; and (iv) extraction of parasitic resistance structures from IC layout. In some embodiments, the IC layout is additionally or alternatively split into groups of rules for processing. Other embodiments are also described.

Abstract: Embodiments disclosed include computer implemented systems and methods comprising multiple computer programs that when used together as part of the system enable the detection of one set of computer files within another set of files without having direct access to the files themselves. A computer program generated unique fingerprint for each set of files that is a condensed representation of that file that ensures no reverse engineering is possible from its use. Another computer program serves as a public repository to securely store fingerprints from multiple sources (e.g. companies).Additionally, another computer program is used to analyze the two or more file sets and produces a report that shows whether files in one set are contained in the other.