Abstract: Systems and methods for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two smaller chips are interconnected to a larger third chip on both sides thereof, and further, with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Another embodiment provides a method for stacking chips where two smaller chips are interconnected to a larger third chip on both sides thereof, and further, with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another embodiment is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.

Abstract: A flash memory configuration and access method having a particular conversion method that uses the page or the sector in each flash memory block instead of the block that is commonly used as the base of the data conversion storage to store data. When data is written into the physical flash block of the flash memory, the original logic sector information can be preserved. The data is written into the same block of the flash memory in a manner according to the sequence as it is received instead of the sequence of the logic sector. Therefore, the block position does not move to refresh the block content until the physical block is full. Consequently, the number of times to move the physical block of the flash memory can be reduced to increase the lifetime of the flash memory. Moreover, since the number of times to erase is reduced, so that the writing speed can speed up to improve the operation efficiency.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.

Abstract: A multi-function interface module having at least one interface and a controller for manipulating input and output data.

Abstract: A memory purge system destructively purges the memory circuits of a memory device. The system includes a power supply for supplying a selectable voltage and current. Switching circuits electrically connect the power supply to the memory circuits of the memory device. A controller selects a voltage and current supplied by the power supply and activates the switching circuit to apply the voltage and current to the memory circuits. The controller determines whether the memory circuits have been destroyed by monitoring current flow into the memory circuits.

Abstract: A multi-function interface module having at least one interface and a controller for manipulating input and output data.

Abstract: A method and structures for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One aspect is a stack of two chips with a preformed interconnecting support connecting the two chips and with space for mounting a third chip to at least one of the other two chips in an interstitial space between the two chips and inside the support. Another aspect is a chip stack where two smaller chips are interconnected a larger third chip on both sides thereof and further with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another aspect is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.

Abstract: A networked system is described in which the majority of data bypass the server(s). This design improves the end-to-end performance of network access by achieving higher throughput between the network and storage system, improving reliability of the system, yet retaining the security, flexibility, and services that a server-based system provides. The apparatus that provides this improvement consists of a network interface, server computer interface, and storage interface. It also has a switching element and a high-layer protocol decoding and control unit. Incoming traffic (either from the network or storage system) is decoded and compared against a routing table. If there is a matching entry, it will be routed, according to the information to the network, the storage interface, or sent to the server for further processing (default). The routing table entries are set up by the server based on the nature of the applications when an application or user request initially comes in.

Abstract: A networked system is described in which the majority of data bypass the server(s). This design improves the end-to-end performance of network access by achieving higher throughput between the network and storage system, improving reliability of the system, yet retaining the security, flexibility, and services that a server-based system provides. The apparatus that provides this improvement consists of a network interface, server computer interface, and storage interface. It also has a switching element and a high-layer protocol decoding and control unit. Incoming traffic (either from the network or storage system) is decoded and compared against a routing table. If there is a matching entry, it will be routed, according to the information to the network, the storage interface, or sent to the server for further processing (default). The routing table entries are set up by the server based on the nature of the applications when an application or user request initially comes in.

Abstract: A module incorporating a flash memory and a flash memory controller. The flash memory controller receives data via a first interface which can be a PCMCIA type interface. The data is then stored in the flash memory. The controller is adapted to be able to selectively recall the data from the flash memory and transmit the data to one or more recipient devices via the PCMCIA type interface or by an alternate interface. The module incorporates a user input device that, when manipulated by the user, induces the controller to send the data via the alternate interface. In one embodiment, the alternate interface is comprised of a GSM interface which allows data stored in the flash memory to be transmitted via a cellular telephone to a pre-selected telephone number by the user manipulating the user input device.