Abstract: A processor includes a time counter and a vector coprocessor for executing vector instructions for statically dispatching vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline. The processor also provides a method for hiding the latency of the vector load instructions.

Abstract: A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching load/store instructions if the required resources are available based on data stored in the time-resource matrix, and wherein execution times for the load/store instructions use a time count from the time counter to specify when the load/store instructions may be provided to a load-store unit pipeline. The execution times of the load instruction is based on the data cache hit latency time. A delay of the load/store instruction causes the load/store instruction to be replayed with known or estimated time. A load-store unit employs multiple bank queues to access multiple data banks of a data cache.

Abstract: A processor includes a time counter and a time-resource matrix and statically dispatches instructions if the resources are available based on data stored in the time-resource matrix. Execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution of a second instruction to a functional unit may be replayed due to the throughput time of a first instruction to the same functional unit. A busy bit and next available time of the functional unit are set when the first instruction is sent to the functional unit are the indication to replay the second instruction.

Abstract: A processor includes a time counter and a time-resource matrix and statically dispatches speculative and in-order instructions. The time counter increments periodically, for example, every clock cycle, and the resulting count is used to statically schedule instruction execution. The processor includes a speculative register rename unit and a non-speculative register rename unit to allow certain types of instructions to be executed speculatively while other instructions are executed non-speculatively.

Abstract: A processor includes a loop detection unit to detect a phantom-loop based on the resources reserved for execution of the phantom loop. The processor executes the phantom loop by reading source operand data on a first iteration of the loop and writing back data on the last iteration of the loop while allowing instructions after the loop to be concurrently executed.

Abstract: A processor includes a time counter and at least one execution slice that is comprised of an instruction decode unit, a time-resource matrix unit, an issue unit, an execution queue, and a functional unit. An instruction is issued to the execution queue to execute at a future time depending on the availability of resources specified in the time-resource matrix, wherein the future time is a time defined by a time count from a periodically incremented time counter.

Abstract: A processor includes a time counter and a vector coprocessor for executing vector instructions for statically dispatching vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline. The processor also provides a method for hiding the latency of the vector load instructions.

Abstract: A processing system includes a time counter, a block of memory and register files, a first processor core and a second processor core, and wherein the processor core includes a register scoreboard and provides a method for statically dispatching instructions with preset execution times based on a write time of a register in the register scoreboard and the time counter provided to an execution pipeline. The processing system also includes method for comparing and validating the functional safety of the processor cores.

Abstract: A processor includes a time counter and a time-resource matrix and statically dispatches speculative and in-order instructions. The time counter increments periodically, for example, every clock cycle, and the resulting count is used to statically schedule instruction execution. The processor includes a speculative register rename unit and a non-speculative register rename unit to allow certain types of instructions to be executed speculatively while other instructions are executed non-speculatively.

Abstract: A processor includes a plurality of register sets of a register file, and a plurality sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of instruction. The register sets and functional units are organized as odd and even sets. Shared buses may also be employed. The processor may also include a time counter and a time-resource matrix and provides a method for statically dispatching instructions.

Abstract: A processor includes a time counter, a vector coprocessor, and a vector data buffer for executing vector load and store instructions. The processor handles unit, stride or indices of data elements of a vector register. The vector data buffer includes crossbar switches for coupling between a plurality of data elements of a vector register and a plurality of data banks of the vector data buffer.

Abstract: A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching instructions if the resources are available based on data stored in the time-resource matrix, and wherein execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction and subsequent dependent instructions to be statically replayed at a later time using the same time count.

Abstract: A processor includes a time counter and a register scoreboard and provides a method for statically dispatching custom or extended instructions with preset execution times based on a write time of a register in the register scoreboard and the time counter provided to an execution pipeline.

Abstract: A processor includes an instruction issue unit that receives a first instruction, and issues the first instruction with a write time, which for a load instruction corresponds to a data cache latency time or to a non-cacheable latency time of a non-cacheable predictor. The non-cacheable predictor includes a tag array and data array with a plurality of entries to predict non-cacheable latency times of non-cacheable load instructions. The non-cacheable predictor can be implemented as a direct map, an N-way associative cache, or a fully associative cache.

Abstract: A processor includes a time counter, a vector coprocessor, and an extended vector register file for executing vector instructions and extending the data width of vector registers. The processor statically dispatches vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline.

Abstract: A processor includes a branch execution unit to detect different loop types based on the number of instructions in the loop and generates a predicted loop count to write to an entry of a branch target buffer (BTB). The different detected loop types are executed in a plurality of instruction queues in the processor depending on the loop type, which is a function of the loop size.

Abstract: A processor includes a time counter and a vector coprocessor for executing vector instructions and providing a method for statically dispatching vector instructions with preset execution times based on a write time of a register in a coprocessor register scoreboard and a time counter provided to a vector execution pipeline.

Abstract: A processor includes a time counter and a time-resource matrix and statically dispatches baseline and extended instructions. The processor includes a plurality of register sets of a register file and a plurality of sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of baseline and extended instructions.

Abstract: A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching load/store instructions if the required resources are available based on data stored in the time-resource matrix, and wherein execution times for the load/store instructions use a time count from the time counter to specify when the load/store instructions may be provided to a load-store unit pipeline. The execution times of the load instruction is based on the data cache hit latency time. A delay of the load/store instruction causes the load/store instruction to be replayed with known or estimated time. A load-store unit employs multiple bank queues to access multiple data banks of a data cache.

Abstract: A processor includes a time counter and a time-resource matrix and statically dispatches instructions if the resources are available based on data stored in the time-resource matrix. Execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution of a second instruction to a functional unit may be replayed due to the throughput time of a first instruction to the same functional unit. A busy bit and next available time of the functional unit are set when the first instruction is sent to the functional unit are the indication to replay the second instruction.