Abstract: A digital logic simulation/emulation system (20) operates in an engaged operating mode in which a digital-logic simulation process (22) transmits stimulation-control data to a hardware pod (32) for controlling stimulation of a digital logic circuit. In response to the stimulation-control data, the hardware pod (32) performs a stimulation-response cycle, and then sends response data from the digital logic circuit to the simulation process (22). The simulation process (22) and the hardware pod (32) may also operate in a disengaged operating mode in which each operates independently of the other without exchanging stimulation-control data or response data. Operation of the system (20) in the disengaged mode commences if a disengagement event occurs in the hardware pod (32). Operation of the system (20) in the disengaged mode terminates if the simulation process (22) sends stimulation-control data to the hardware pod (32), or if the hardware pod (32) sends response data to the simulation process (22).

Abstract: A digital logic simulation/emulation system, that includes a hardware pod having a configurable-logic IC arranged to provide a plurality of stimulus/response cells, is adapted for coupling to a digital logic circuit. The stimulus/response cells, which provide stimulus signals to the digital logic circuit, connect to form a shift-register for downloading stimulus-control data, and for uploading response data during a stimulation-response cycle. A logic-configuration library stores configuration-data for establishing a bit-slice architecture for the stimulus/response cells. To facilitate preparing the configuration-data, the system also includes a configurable-logic-specification process having a GUI user interface. The logic-specification process assigns pre-established, bit-slice configuration data for each logic-function cell to specific locations throughout a configurable-logic IC to achieve swift compilation of configuration data.