Abstract: The invention relates to a NAND stack EEPROM that with random programming capability. In one embodiment, dynamic program inhibit is used to achieve random programming the memory cells within a NAND stack.

Abstract: The invention relates to a non-volatile, static random access memory (nvSRAM) in which there are at least two, non-volatile memory cells associated with each SRAM memory cell. The non-volatile memory cells are capable of being programmed with whatever bit of information is present in the SRAM at two different times. In one embodiment, the non-volatile memory cells are capable of being randomly programmed, i.e., programmed in any order. Further, the bits of data programmed into the non-volatile memory cells can be recalled in any order, i.e., randomly recalled.

Abstract: A wireless communication system for receiving and transmitting serial bus data packets in conformance with a CSMA/CA protocol implemented in an ACCESS.bus serial bus data protocol which may accommodate either RF or IR transmissions for peer-to-peer communications between computers and between peripherals, as well as computer-to-peripheral and peripheral-to-computer communications.

Abstract: An FM/FSK Transceiver for a wireless communications interface is disclosed which employs an offset phase lock loop which is accelerated into phase lock by a sweep signal to avoid data degradation, and which includes a feed forward compensation to accommodate a broadband response from DC to above 10 MHz in the exchange of information between computers, computers and peripheral equipments, and between peripheral equipments.

Abstract: The invention relates to a non-volatile, static random access memory (nvSRAM) device that is capable of high speed copying of the data in the static random access portion of the device into the non-volatile portion of the device after the detection of possible loss of power. This is accomplished by preparing the non-volatile portion for receiving a bit of data from the SRAM portion before the possible loss of power is detected, i.e., pre-arming the device. In one embodiment, the pre-arming is accomplished by erasing the non-volatile portion during the time when the power supply is stable and data can be transferred between the SRAM portion and the exterior environment. In another embodiment, pre-arming is accomplished by erasing the non-volatile portion immediately after power has been provided to the device and data from the non-volatile portion has been copied into the SRAM in a recall operation. Another aspect of the invention provides for the decoupling of the erase and store operations.

Abstract: The invention relates to a non-volatile, static random access memory (nvSRAM) device that addresses the consequence of a manufacturing defect that occasionally occurs during mass production of the nvSRAM device and if not addressed, reduces the yield of the production process. The consequence of the defect is termed a store disturb because the execution of a store operation in a defective nvSRAM causes the bit of data retained in the SRAM portion and, in some cases, the nv portion of the nvSRAM to be instable or corrupted. The present invention provides an nvSRAM device in which the controller provides modified signals to the nvSRAM memory portion of the device that address the store disturb phenomena and, as a consequence, improve the yield of the manufacturing process.

Abstract: A semiconductor memory device is disclosed that provides replacement of defective main memory portions with operational redundant memory portions. The device includes fuse circuitry that comprises both nonvolatile and volatile memory portions. Because the fuse circuitry includes a volatile memory portion in addition to a nonvolatile memory portion, additional functionality may be achieved by the fuse circuitry. For example, the volatile portion of the fuse circuitry allows the retention of the nonvolatile portion of the circuitry to be tested using standard testing techniques. In addition, the volatile memory portion provides a way for easily utilizing unused redundant memory. In one embodiment of the present invention, a semiconductor memory device is provided that uses nvSRAM cells as the main storage element in the main memory area, the redundant memory area, and in the fuse circuitry.

Abstract: The present invention provides a non-volatile, static random access memory (nvSRAM) cell with a current limiting feature that prevents current that is provided to the cell or array of cells during a recall operation in which information is transferred from the non-volatile portion of the cell or array to the static random access memory portion of the cell or array from reaching a point that would be detrimental to the cell or array. The current limiting device is located between the nvSRAM cell or array of cells and ground. In one embodiment, the current limiting device includes a variable resistance and a device for modulating the resistance so that the resistance is high at the beginning of a recall operation and decreases thereafter.

Abstract: The present invention provides a computer memory device having a sleep mode characterized by extremely low current consumption and relatively large turn on delay. The invention includes circuitry for disabling current sinking elements internal to said device in response to a sleep signal. In one embodiment, the invention includes circuitry for disconnecting the bit lines and memory cell loads of a nonvolatile static random access memory (nvSRAM) array from a source of power in response to a sleep signal. This embodiment is capable of first transferring the data stored in a volatile portion of the array to a nonvolatile portion of the array before entering sleep mode to prevent loss of the data.

Abstract: One embodiment of the differential sense amplifier of the present includes a pair of amplifier portions, each of which includes a reference branch and an amplifying branch. Each amplifier portion amplifies one input signal of the differential input signal applied to the differential sense amplifier by an amount related to the difference between the applied input signal and a reference signal established by the reference branch of the amplifier portion. The input signals are cross-coupled between the amplifier portions so that each input signal is applied to the reference branch of one amplifier portion and to the amplifying branch of the other amplifier portion. Separate reference nodes and reference signals are established for each amplifier portion. A change in the differential input signal creates correspondingly opposite changes in the magnitude of the reference signal and the input signal applied to the amplifying branch of both amplifier portions to provide greater gain and sensitivity.

Abstract: A non-volatile random access memory (NVRAM) cell of condensed size employs a pair of programmable threshold voltage devices, e.g. MNOS (metal nitride oxide semiconductor), SNOS (silicon nitride oxide semiconductor), SONOS (silicon oxide-nitride-oxide semiconductor) or floating gate transistors, in which different threshold voltage levels are established in accordance with the data signal levels existing on the data nodes of a flip flop, when the volatile data is stored in the programmable devices. During recall of the non-volatile stored data to the data nodes of the flip flop, the programmable devices actively conduct current to the data nodes to set the flip flop in the same state that existed when the data was stored. Power is supplied to the flip flop independently of the power supplied to the programmable devices. A single polysilicon conductor forms gates of transistors which connect the programmable devices to the data nodes and the gates of the flip flop transistors.

Abstract: A current mirror sense amplifier includes current control devices connected in series with each pair of transistors forming a reference branch and an amplifying branch of the amplifier. The control devices are connected and biased in a cross latched manner, and when the reference and amplifying branches respond to a differential input signal, the conductivity of the control devices regeneratively changes until the current through both branches is ultimately terminated and the output signal attains a level substantially at the level of one of the supply voltages, Vcc and Vss. The sense amplifier also includes resetting devices for reestablishing the initial conductivity states of the branches and the control devices, in order to allow the sense amplifier to respond to a new differential input signal. Biasing transistors establish initial bias levels for the control devices which prevent them from regenerating into the opposite conductive until a differential input signal is applied.

Abstract: A single ended sense amplifier senses whether or not a memory cell in an array conducts current from a bit line conductor to which the sense amplifier is connected. A first stage of the sense amplifier includes a number of separately biased transistors which establish a lower voltage level at a node when the cell conducts current than the higher voltage level at the node when the cell does not conduct current. A second stage of the sensed amplifier includes transistors connected in an inverting arrangement to receive the signal from the node and supply an output signal at an output terminal in response thereto. An equalizing transistor is selectively connected between the node and the output terminal and establishes a high gain bias point voltage at the node when conductive. The high gain bias point in intermediate the higher and lower voltages established at the node by the first stage.