Abstract: Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprises a plurality of hardware gates, each of which is programmable so as to correspond to and emulate an element in said logic circuit. Each hardware gate has an output and at least two inputs. A selectively operable interconnection system is provided for establishing a connection between the output of any hardware gate and an input of any hardware gate. A multiplexing system is also provided for operating the interconnection system and determining which, and when, each connection is made between the output of any hardware gate and an input of any hardware gate.