Abstract: The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actua

Abstract: The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.

Abstract: The present invention discloses a halo test method for an optical chip in an integrated circuit. A captured image array is processed as a circle by: dividing the array into circular patterns on the basis of the radius, reconstructing the circular patterns into a two-dimensional array according to coordinates, and then performing corresponding operations on the obtained array to obtain a desired value. By the halo test method for an optical chip in an integrated circuit provided in the present invention, without increasing any extra hardware cost and under the primary test conditions, the technical problem in the prior art that there is no well-developed method and algorithm for testing halo on a fingerprint on display (FOD) chip is solved.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.

Abstract: A compression method for compressing an original test file is disclosed. The compression method includes the following steps: defining type modules; scanning the original test file line by line in bytes and matching data of the original test file with the type modules to determine types of the data; compressing continuous data of the same type in lines and representing each compressed portion with a thumbnail. The compression method enables a browser to read test files with a fast speed by compressing test files according to the types of data.

Abstract: A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (210), a peripheral circuit (220), a circuit of special function (230), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (240, 250). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.