Patents Assigned to Sip-Societa Italiana per l'Esercizio delle Telecommunicazioni P.A.
  • Patent number: 5321793
    Abstract: A low-delay audio signal coding system, using analysis-by-synthesis techniques, has circuitry for adapting the spectral parameters and the prediction order of synthesis filters, and of perceptual weighting filters in the order at each frame, starting from the reconstructed signal relevant to the previous frame. In the case of a CELP coder, gain controls are also provided to adapt, starting from the reconstructed sinal, a factor, bound to the average power of the input signal, of the gain by which the innovation vectors are weighted.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: June 14, 1994
    Assignee: SIP--Societa Italiana per l'Esercizio delle Telecommunicazioni P.A.
    Inventors: Rosario Drogo De Iacovo, Roberto Montagna, Daniele Sereno
  • Patent number: 5319447
    Abstract: The video control circuit is particularly adapted to multimedia applicati, wherein image transmission services are offered in addition to usual telephone speech and data transmission services. The circuit is capable of processing both photographic and graphic video images, satisfying both the relevant CCIR standards and the specifications proper to personal computers, VGA EGA, etc. so as to allow the representation of either types of images on an only type of display. To this end, it generates both timings proper to the CCIR standards, for a resolution of 720 columns per 480 lines, with an upper representation limit of graphic planes of 1024 columns per 1024 lines.
    Type: Grant
    Filed: February 11, 1993
    Date of Patent: June 7, 1994
    Assignee: SIP-Societa Italiana per l'Esercizio delle Telecommunicazioni P.A.
    Inventors: Pierangelo Garino, Giovanni Ghigo, Mauro Marchisio, Giovanni Pucci, Alfredo Rinaudo
  • Patent number: 5309449
    Abstract: An electronic circuit for generating error detection codes in digital sigs organized into serial data blocks, which derives the error code from the coefficients of a remainder polynomial obtained from the division of a dividend polynomial, whose coefficients are the bits of each serial block, and a convenient divisor polynomial. The circuit has a shift register wherein at the beginning of each serial data block the reset and the first datum load are performed in a single clock interval.
    Type: Grant
    Filed: February 20, 1991
    Date of Patent: May 3, 1994
    Assignee: Sip-Societa Italiana per l'Esercizio delle Telecommunicazioni P.A.
    Inventors: Marco Gandini, Giovanni Ghigo, Mauro Marchisio