Patents Assigned to Sires Labs Sdn. Bhd.
  • Patent number: 7233196
    Abstract: An electrical circuit is disclosed that is capable of improving the power supply rejection ratio of a standard bandgap reference while maintaining the temperature coefficient of the standard design. One embodiment of the circuit comprises a bandgap reference voltage generator, an operational amplifier, a transistor, a voltage divider, a startup network, and a self-biasing network that provide a voltage reference with improved characteristics.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 19, 2007
    Assignee: Sires Labs Sdn. Bhd.
    Inventor: Arshad Suhail Farooqui
  • Patent number: 7202726
    Abstract: A voltage-controlled oscillator design is disclosed that provides greater tuning range than a prior art differential amplifier design using “varactor” diodes. The design employs CMOS capacitors to replace varactor diodes. The CMOS capacitors are formed from PMOS transistors in which the drain of the transistor is electrically connected to the source of the same transistor, so that voltage-dependant capacitors are formed between the gate-to-source terminals and the gate-to-drain terminals of the PMOS transistor. Secondly, the monolithic inductors employed in the prior art are replaced by “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor, where the potential at the drain of the NMOS transistor is held below that of the second terminal of the resistor by at least the threshold, or turn-on voltage, of the transistor. The resistor/transistor combination acts inductively at the frequency of oscillation of interest.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: April 10, 2007
    Assignee: Sires Labs Sdn. Bhd.
    Inventors: Mohan Krishna Kunanayagam, Shubha Sharma
  • Patent number: 7135932
    Abstract: A transimpedance amplifier, which is useful as an optical fiber preamplifier, is disclosed. The illustrative embodiment exhibits four characteristics. First, it minimizes the equivalent input noise current. Second, it has a wide bandwidth. Third, it has a reasonably large output voltage, and fourth, it is stable over wide temperature and voltage ranges. The illustrative embodiment comprises a transimpedance stage and a gain stage. Both stages employ a pure NMOS design which contributes to the above four advantages. Bandwidth is further increased over the prior art by the use of inductive loads. The inductive loads of the illustrative embodiment are not physical inductors, but transistor-based “active” inductors: the combination of a resistor connected in series with the gate of an NMOS transistor.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: November 14, 2006
    Assignee: Sires Labs Sdn. Bhd.
    Inventors: Nasir Abdul Quadir, Farrah Azlin Binti Alias, K. Selvarajah K. Krishnarajoo
  • Publication number: 20060067713
    Abstract: An optical receiver is disclosed that exhibits an improved phase margin and substantially constant output in response to changes in operating conditions (e.g., temperature, process, etc.). In accordance with the illustrative embodiment, a common-mode feedback comparison is performed prior to conversion of the signal from single-ended to differential voltage. When the common-mode feedback comparison is performed in this way, there are fewer amplifiers in the signal path and the phase margin of the common-mode feedback loop is increased. In addition, as the common-mode feedback is performed at the first stage of the transimpedance amplifier, the gain response of the transimpedance amplifier remains substantially constant in response to changes in temperature, input current range, and for different integrated circuit fabrication processes.
    Type: Application
    Filed: June 28, 2005
    Publication date: March 30, 2006
    Applicant: Sires Labs Sdn. Bhd.
    Inventors: Arshad Farooqui, Lee Ying