Abstract: An arrangement (100) is provided. The arrangement comprises an integrated circuit package (2). The integrated circuit package comprises a first side (2a) which comprises interconnect elements, and a second side (2b) which is opposite to the first side (2a). The integrated circuit package further comprises at least one antenna element (25), and a heatsink element (1) arranged on the second side (2b) of the integrated circuit package (2). The heat sink element comprises at least one passage (10). The at least one passage (10) extends through the heatsink element (1). A first opening (13) of the at least one passage (10) is arranged at a respective antenna element (25) of the at least one antenna element. The at least one passage (10) is configured to increase the gain of the respective antenna element (25).

Abstract: Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.

Abstract: An integrated circuit package is provided. The integrated circuit package comprises a transceiver radio-frequency integrated circuit, RFIC, and at least one antenna array formed in a redistribution metal layer of the integrated circuit package, and is arranged in a fan-out area of the RFIC. The at least one antenna array comprises at least one crossed dipole antenna. Each crossed dipole antenna comprises a first dipole comprising two first legs, and a second dipole comprising two second legs, and two leg pairs, each leg pair comprising one first leg of the first dipole and one second leg of the second dipole, and two feed lines. Each feed line is coupled to a respective leg pair at a center of the crossed dipole antenna. At least a part of each feed line is arranged between the two leg pairs.

Abstract: The present invention relates to an antenna device comprising an antenna part having a patch with several edges, a first transmit path connected to a first connection port at a first edge of the patch, and a second transmit path connected to a second connection port at the first edge of the patch. The first and second connection ports are located at a distance from each other along the first edge, and a first transmitter and a second transmitter are connected to the antenna part. The first transmit path comprises a first signal combiner connected to the first and second transmitters and to the first connection port. The second transmit path comprises a second signal combiner connected to the first and second transmitters and to the second connection port. The first signal combiner is arranged to generate a difference between signals originating from the first and second transmitters. The second signal combiner is arranged to generate a sum of the signals originated from the first and second transmitters.

Abstract: Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.

Abstract: The present invention relates to an antenna device comprising an antenna part having a patch with several edges, a first transmit path connected to a first connection port at a first edge of the patch, and a second transmit path connected to a second connection port at the first edge of the patch. The first and second connection ports are located at a distance from each other along the first edge, and a first transmitter and a second transmitter are connected to the antenna part. The first transmit path comprises a first signal combiner connected to the first and second transmitters and to the first connection port. The second transmit path comprises a second signal combiner connected to the first and second transmitters and to the second connection port. The first signal combiner is arranged to generate a difference between signals originating from the first and second transmitters. The second signal combiner is arranged to generate a sum of the signals originated from the first and second transmitters.

Abstract: An integrated circuit package is provided. The integrated circuit package comprises a transceiver radio-frequency integrated circuit, RFIC, and at least one antenna array formed in a redistribution metal layer of the integrated circuit package, and is arranged in a fan-out area of the RFIC. The at least one antenna array comprises at least one crossed dipole antenna (10). Each crossed dipole antenna comprises a first dipole comprising two first legs (11), and a second dipole comprising two second legs (12), and two leg pairs (10a, 10b), each leg pair comprising one first leg of the first dipole and one second leg of the second dipole, and two feed lines (20a, 20b). Each feed line is coupled to a respective leg pair at a center (15) of the crossed dipole antenna. At least a part of each feed line is arranged between the two leg pairs.

Abstract: An arrangement (100) is provided. The arrangement comprises an integrated circuit package (2). The integrated circuit package comprises a first side (2a) which comprises interconnect elements, and a second side (2b) which is opposite to the first side (2a). The integrated circuit package further comprises at least one antenna element (25), and a heatsink element (1) arranged on the second side (2b) of the integrated circuit package (2). The heat sink element comprises at least one passage (10). The at least one passage (10) extends through the heatsink element (1). A first opening (13) of the at least one passage (10) is arranged at a respective antenna element (25) of the at least one antenna element. The at least one passage (10) is configured to increase the gain of the respective antenna element (25).