Abstract: The sintered body including silicon oxide and carbon, wherein the sintered body has a D band peak at a wave number of 1,311 cm?1 to 1,371 cm?1 and a G band peak at a wave number of 1,572 cm?1 to 1,632 cm?1 in a Raman spectrum, and wherein the D band peak or the G band peak have a higher intensity than a fifth peak present at a wave number of 1,027 cm?1 to 1,087 cm?1 in the Raman spectrum, is disclosed.

Abstract: The sintered body including boron carbide, wherein the sintered body includes a zone, in which a volume ratio of grains having a grain size of greater than 30 ?m and 60 ?m or less is in a range of 50% to 70% based on a total volume of grains, as observed on a surface of the sintered body, is disclosed.

Abstract: Embodiments relate to a polishing pad, which comprises a window having a hardness similar to that of its polishing layer. Since the polishing pad comprises a window having a hardness and a polishing rate similar to those of its polishing layer, it can produce an effect of preventing scratches on a wafer during a CMP process. In addition, the polishing layer and the window of the polishing pad have a similar rate of change in hardness with respect to temperature, so that they can maintain a similar hardness despite a change in temperature during the CMP process.

Abstract: The present disclosure provides a polishing pad, which may maintain polishing performances required for a polishing process, such as a removal rate and a polishing profile, minimize defects that may occur on a wafer during the polishing process, and polish layers of different materials so as to have the same level of flatness even when the layers are polished at the same time, and a method for producing the polishing pad. In addition, according to the present disclosure, it is possible to determine a polishing pad, which shows an optimal removal rate selectivity along with excellent performance in a CMP process, through the physical property values of the polishing pad without a direct polishing test.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.

Abstract: A blank mask includes a light transmissive substrate and a multilayer comprising a light shielding layer and a phase shift layer disposed between the light transmissive substrate and the light shielding layer. The phase shift layer includes an upper surface facing the light shielding layer and a side surface connected to the upper surface, such that the light shielding layer is disposed on the upper surface and the side surface of the phase shift layer. When viewed from a top surface of the multilayer, the multilayer includes a central portion and an outer portion surrounding the central portion. The outer portion has a curved upper surface, which greatly suppresses damage to the phase shift layer by a cleaning solution and effectively reduces a frequency of particle generation at edges of the phase shift layer and the light shielding layer.

Abstract: A plasma etching apparatus includes a chamber configured to generate plasma, an electrostatic chuck disposed in the chamber, and a focus ring placed on the electrostatic chuck and configured to support an object to be etched. The focus ring includes a seating part and a body part. A seating surface is provided on at least a portion of the seating part configured to seat the object to be etched thereon. The focus ring further includes a step provided between the seating part and the body part. The body part includes a body area and a chucking reinforcement area. The body area includes a first corrosion resistant layer, and the chucking reinforcement area includes a second corrosion resistant layer. The second corrosion resistant layer is thinner than the first corrosion resistant layer, and has a minimum thickness of 1 mm or more.

Abstract: A focus ring for mounting an etching target in a plasma etching device, includes a seating portion, including a seating surface configured to accommodate the etching target; and a main body, formed on an outer circumference of the seating portion, comprising a groove portion having a groove disposed in an upper surface of the main body. A height of an upper surface of the groove portion is lower than a maximum height of the upper surface of the main body.

Abstract: A blank mask includes a light transmissive substrate, and a light-blocking layer, disposed on the light transmissive substrate, comprising a transition metal and either one or both of oxygen and nitrogen. An average value of grain sizes of a surface of the light-blocking layer ranges from 14 nm to 24 nm.

Abstract: A shadow mask includes a mask including one surface, another surface, and an opening that passes from one surface to the other, and a shutter provided on the one surface of the mask and configured to adjust a size of the opening, wherein the shutter is configured to move from an edge to a center of the opening to adjust the size of the opening, and the shadow mask is applied in manufacturing a blank mask for a semiconductor lithography process.

Abstract: A blank mask includes a light-transmitting substrate; and a light-shielding film on the light-transmitting substrate. The light-shielding film includes a transition metal and oxygen, and a scum formation time required to generate scum is 120 minutes or more when light with a wavelength of 172 nm and an intensity of 10 kJ/cm2 is applied on the light-shielding film.

Abstract: A composition for semiconductor processing, includes abrasive particles surface-modified with an amino silane-based compound; a copper erosion inhibitor, including an azole-based compound; a copper surface protectant, including a compound having a betaine group and a salicylic group or a derivative thereof; and a surfactant, including fluorine in a molecule thereof. A surface of the surface-modified abrasive particles comprises an amino silane group.

Abstract: A composition for semiconductor processing includes abrasive particles, and a dishing control additive, comprising a first dishing control additive and a second dishing control additive. The first dishing control additive includes a compound having a betaine group and a salicylic group or a derivative thereof, and the second dishing control additive includes an azole-based compound. The first dishing control additive includes 0.07 parts by weight or more based on 100 parts by weight of the abrasive particles, and the second dishing control additive includes 0.13 parts by weight or less based on 100 parts by weight of the abrasive particles.

Abstract: Disclosed is a method for producing a polishing pad, the method comprising the steps of: providing a polishing layer; forming a first through-hole penetrating the polishing layer; providing a support layer facing the polishing layer; interposing an adhesive layer between the polishing layer, which has the first through-hole, and support layer, and adhering the polishing layer and support layer to each other by means of the adhesive layer; forming, with the first through-hole as a reference point, a third through-hole penetrating the adhesive layer on a set area thereof, and a second through-hole penetrating the support layer on a set area thereof; and inserting a window inside the first through-hole.

Abstract: Embodiments relate to a porous polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polishing pad can be adjusted in light of the volume thereof. Thus, the plurality of pores have an apparent volume-weighted average pore diameter in a specific range, thereby providing a porous polishing pad that is excellent in such physical properties as polishing rate and the like.

Abstract: An extreme ultraviolet photomask includes a conductive layer; a substrate disposed on the conductive layer; a multilayer, comprising different metals alternately stacked on the substrate; a protective layer disposed on the multilayer; a low-reflectance part disposed on a portion of the protective layer, wherein the low-reflectance part comprises a first absorbent layer disposed on the portion of the protective layer, a low-reflectance layer formed on the first absorbent layer, and a first intagliated part formed at the portion where the protective layer is exposed; and a high-reflectance part disposed on another portion of the protective layer, wherein the high-reflectance part comprises a second absorbent layer disposed on the other portion of the protective layer, a high-reflectance layer disposed on the second absorbent layer, and a second intagliated part formed at the other where the protective layer is exposed.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.

Abstract: The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.

Abstract: A method for determining the status of a robot according to an embodiment includes acquiring first data and second data related to an operation of the robot, acquiring a resonance frequency by analyzing the operation of the robot in a frequency region based on the first data related to the operation of the robot, acquiring a first comparison result by comparing the acquired resonance frequency with a reference resonance frequency, when the first comparison result is a threshold value or more, generating a Lissajous figure by DQ transforming a three-phase signal based on the second data related to the operation of the robot, acquiring a second comparison result by comparing the generated Lissajous figure with a reference Lissajous figure, and determining the status of the robot based on at least one of the first comparison result and the second comparison result.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for producing the same. In the porous polyurethane polishing pad, it is possible to control the size and distribution of pores, whereby the polishing performance (i.e., polishing rate) of the polishing pad can be adjusted, by way of employing thermally expanded microcapsules as a solid phase foaming agent and an inert gas as a gas phase foaming agent.