Patents Assigned to SK Hynic Inc.
  • Patent number: 12618893
    Abstract: A reliability measuring apparatus includes an oxide-nitride-oxide-alumina (ONOA) current measuring circuit configured to measure an ONOA current by applying an ONOA current measuring voltage to a selected word line coupled to a selected memory cell in a flash memory and a reliability indicator generator configured to a reliability indicator using the ONOA current measured through the measuring circuit.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: May 5, 2026
    Assignee: SK hynic Inc.
    Inventors: Nam Cheol Jeon, Hea Jong Yang, Tae Un Youn
  • Patent number: 12568829
    Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: March 3, 2026
    Assignee: SK hynic Inc.
    Inventors: Jae Jun Lee, Jong Yeon Kim, Jong Hoon Kim, Ju Heon Yang, Mi Seon Lee
  • Patent number: 12563311
    Abstract: An image processing device includes a memory configured to store a super resolution network trained to output a corrected image based on an input image; and a processor configured to output a super resolution image based on a first image acquired by a first image sensor and a corrected image output from the super resolution network. The super resolution network is a model trained by using second images acquired through a second image sensor, a type of the second image sensor being different from a type of the first image sensor.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: February 24, 2026
    Assignee: SK hynic Inc.
    Inventor: Dong Ik Kim
  • Patent number: 10152252
    Abstract: A memory system includes a memory device including a first and a second group of memory blocks; and a controller suitable for: performing a processing operation corresponding to a plurality of workloads included in transactions received from a host, checking transaction identification information and completion information included in the workloads, storing first workloads among the workloads in the memory blocks included in the first group, corresponding to the identification information and the completion information, and transmitting and storing the first workloads into the memory blocks included in the second group.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: December 11, 2018
    Assignee: SK Hynic Inc.
    Inventors: Do-Hyun Kim, Soong-Sun Shin, Dae-Hong Kim
  • Patent number: 9640426
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: May 2, 2017
    Assignee: SK Hynic Inc.
    Inventors: Il-Cheol Rho, Jong-Min Lee
  • Patent number: 9484344
    Abstract: A semiconductor apparatus includes a reservoir capacitor, and the reservoir capacitor includes a plurality of MOS capacitors serially coupled to one another. The plurality of MOS capacitors are arranged in one well.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: November 1, 2016
    Assignee: SK hynic Inc.
    Inventors: Ji Tai Seo, Yeon Ok Kim
  • Patent number: 9401187
    Abstract: An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to Nth signals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 26, 2016
    Assignee: SK Hynic Inc.
    Inventor: Hyun-Sung Lee
  • Publication number: 20140347909
    Abstract: A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset order in response to an enable signal and an operation clock, and storage blocks suitable for receiving and storing the plurality of fuse status signals in a preset order in response to the selection codes.
    Type: Application
    Filed: December 17, 2013
    Publication date: November 27, 2014
    Applicant: SK hynic Inc.
    Inventor: Sung-Soo CHI
  • Patent number: 8716690
    Abstract: A variable resistor, a nonvolatile memory device and methods of fabricating the same are provided. The variable resistor includes an anode electrode and a cathode electrode, a variable resistive layer including CdS nanoscale particles provided between the anode electrode and the cathode electrode, and an initial metal atom diffusion layer within the variable resistive layer. The variable resistor is a bipolar switching element and configured to be in a reset state when a positive voltage relative to a cathode electrode is applied to the anode electrode, and configured to be in a set state when a negative voltage relative to the cathode electrode is applied to the anode electrode.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 6, 2014
    Assignees: SK Hynic Inc., Korea University Research and Business Foundation
    Inventors: Woong Kim, Yong chan Ju, Seungwook Kim
  • Patent number: 8441870
    Abstract: A data strobe signal output driver includes a trigger block, a predriver block, and a main driver block. The trigger block is configured to receive a first signal, a second signal, a first clock and a second clock, and to output a predrive signal based thereon. The predriver block is configured to receive the predrive signal, a driver off signal and a termination enable signal, and to output a first main drive signal and a second main drive signal based thereon. The main driver block is configured to output a data strobe signal based on the first and second main drive signals.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: May 14, 2013
    Assignee: SK Hynic Inc.
    Inventor: Mi Hye Kim