Patents Assigned to SK Hynix Inc. Gyeonggi-do
  • Patent number: 10163924
    Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc. Gyeonggi-do
    Inventor: Jung Ryul Ahn