Abstract: On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA's entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.

Abstract: This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.

Abstract: A system and related method, including memory and processing circuitry, which is to receive data and corresponding expected error-detecting code value. The processing circuitry processes the data in at least two portions by calculating and storing, in memory, an error-detecting code value for the respective portion. The processing circuitry is then to calculate an overall error-detecting code value based on the respective error-detecting code values for the at least two portions. When the overall error-detecting code value does not match the expected error-detecting code value the processing circuitry is to correct at least one portion and process the corrected portions by calculating an updated error-detecting code value for a respective one of the corrected portions and calculating an updated overall error-detecting code value based on the updated error-detecting code value for each corrected portions and the stored error-detecting code values.

Abstract: A method and controller for operating a memory system in communication with a host. The method and controller logically arrange a sequence of reclaim sub-groups within a memory device. The method and controller process the reclaim sub-groups according to the sequence to control the memory device to perform garbage collection on the reclaim sub-groups in the memory device. In the sequence, the reclaim sub-groups are processed during the garbage collection such that at least one re-ordered data sequence in the sequence of the reclaim sub-groups being processed has re-ordered valid data that is not clumped.

Abstract: An apparatus comprises a controller comprising an interface comprising circuitry to communicate with a host computing device; and a relocation manager comprising circuitry, the relocation manager to provide, for the host computing device, an identification of a plurality of data blocks to be relocated within a non-volatile memory; and relocate at least a subset of the plurality of data blocks in accordance with a directive provided by the host computing device in response to the identification of the plurality of data blocks to be relocated.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to an interposer with step features used to electrically couple stacked dies. In embodiments, the step features may appear as a ziggurat shape to one or more sides of the interposer, which may be referred to as a ziggurat interposer. The interposer may have electrical routing disposed within to electrically couple the first face of the one of the step features with a die.

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

Abstract: This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.

Abstract: Read Quality of Service in a solid state drive is improved by allowing a host system communicatively coupled to the solid state drive to control garbage collection in the solid state drive. Through the use of controlled garbage collection, the host system can control when to start and stop garbage collection in the solid state drive and the number of NAND dies engaged in garbage-collection operations.

Abstract: A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.

Abstract: Mechanisms for prioritizing read commands over write commands to a storage device are provided, the mechanisms comprising: determining counts of read commands targeting a plurality of portions of the storage device; calculating a threshold based on a function of an average of the counts of read commands targeting the plurality of portions of the storage device; determining that a count of read command(s) targeting one of the plurality of portions of the storage device meets the threshold; and in response to determining that the count of read command(s) targeting the one of the plurality of portions of the storage device meets the threshold, prioritizing a read command to access the one of the plurality of portions of the storage device over at least one write command.

Abstract: Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.

Abstract: Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

Abstract: Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.

Abstract: Systems and methods for operating a low-density parity-check (LDPC) bit-flipping decoder are disclosed herein. An LDPC codeword is received, and each bit in the LDPC codeword is classified as either a high-confidence bit or a low-confidence bit based on at least one criterion. The LDPC codeword is iteratively processed over a plurality of iterations based on parity check equations associated with each bit of the LDPC codeword to generate a processed LDPC codeword. For each iteration of the plurality of iterations, the iterative processing includes flipping at least one bit of the LDPC codeword, while preventing, for a first n number of the plurality of iterations, bits classified as high-confidence bits from comprising more than 33% of the total number of flipped bits. The processed LDPC codeword is decoded.

Abstract: This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.

Abstract: This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.

Abstract: A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix.

Abstract: A device and related method, the device including memory and processing circuitry. The memory includes sets of source memory bands and a defragmentation destination memory band. Each set of source memory bands includes source memory bands and at least one portion of each source memory band stores valid data. The processing circuitry determines a merit score corresponding to each source memory band based on one or more characteristics of portions of data of each corresponding source memory band and determines, for each set of source memory bands, a respective source memory band that corresponds to a second-highest merit score. The processing circuitry identifies a set of source memory bands that includes a source memory band corresponding to a highest second-highest merit score and stores at least one portion of valid data from the source memory bands of the identified set of source memory bands to the defragmentation destination memory band.

Abstract: A non-transitory computer-readable medium and related method, including processing circuitry, which performs in-order error correction code construction. The processing circuitry receives a first plurality of matrices. The processing circuitry is to generate a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices. The processing circuitry then generates a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices. Each respective weight indicative of respective extensibility for each matrix of the second plurality of matrices is determined based on the third plurality of matrices. At least one matrix from the second plurality of matrices is then selected by processing circuitry based on the determined weights. The processing circuitry then generates an error correction code based on one of the at least one selected matrix.