Patents Assigned to SK HYNIX SYSTEM IC INC.
-
Patent number: 11908916Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.Type: GrantFiled: April 30, 2021Date of Patent: February 20, 2024Assignee: SK hynix system ic Inc.Inventors: Soon Yeol Park, Yoon Hyung Kim, Yu Shin Ryu
-
Patent number: 11705482Abstract: A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.Type: GrantFiled: December 23, 2022Date of Patent: July 18, 2023Assignee: SK Hynix system ic Inc.Inventors: Kyung Wook Kwon, Mun Young Lee, Myoung Kyun Choi
-
Patent number: 11569343Abstract: A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.Type: GrantFiled: January 6, 2021Date of Patent: January 31, 2023Assignee: SK HYNIX SYSTEM IC INC.Inventors: Kyung Wook Kwon, Mun Young Lee, Myoung Kyun Choi
-
Patent number: 11183252Abstract: A dynamic voltage supply circuit of a nonvolatile memory device includes a voltage amplification/output circuit and a dynamic voltage output circuit. The voltage amplification/output circuit receives a first clock signal and a second clock signal to generate a dynamic supply voltage greater than a supply voltage while the first clock signal has a “low” level. The dynamic voltage output circuit outputs the dynamic supply voltage while the first clock signal has a “low” level and outputs a ground voltage while the first clock signal has a “high” level.Type: GrantFiled: February 11, 2020Date of Patent: November 23, 2021Assignee: SK Hynix system ic Inc.Inventor: Hyun Min Song
-
Patent number: 11158720Abstract: A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region. A second insulation pattern is disposed over the second region of the semiconductor region. The second insulation pattern has a thickness greater than a thickness of the first insulation pattern. A gate electrode is disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region.Type: GrantFiled: February 6, 2019Date of Patent: October 26, 2021Assignee: SK hynix system ic Inc.Inventors: Soon Yeol Park, Yoon Hyung Kim, Yu Shin Ryu
-
Patent number: 11133070Abstract: A nonvolatile memory device includes a nonvolatile memory cell including a first cell transistor and a second cell transistor electrically coupled to a bit line in parallel and configured to respectively have a first physical size and a second physical size, a cell transistor selector coupled between the nonvolatile memory cell and a ground voltage terminal to control electrical connections between the first cell transistor and the ground voltage terminal, and between the second cell transistor and the ground voltage terminal, and a read voltage selection circuit suitable for selectively supplying one of a first read voltage and a second read voltage to the bit line.Type: GrantFiled: June 16, 2020Date of Patent: September 28, 2021Assignee: SK hynix system ic Inc.Inventor: Hyun Min Song
-
Patent number: 11114450Abstract: A one-time programmable (OTP) memory device includes a plurality of unit cells which are respectively located at cross points of word lines and bit lines. Each unit cell includes a selection transistor and a storage transistor coupled in series. The selection transistor includes a drain region and a common junction region separated by a first channel region and includes a selection gate structure disposed on the first channel region. The storage transistor includes a source region and the common junction region separated by a second channel region and includes a floating gate structure disposed on the second channel region. A length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction.Type: GrantFiled: January 24, 2019Date of Patent: September 7, 2021Assignee: SK hynix system ic Inc.Inventor: Kwang Il Choi
-
Patent number: 10727063Abstract: A method includes forming a blocking pattern on a buffer insulation layer disposed over a first region in a semiconductor region of a second conductivity type, forming an ion implantation mask pattern having an opening over the buffer insulation layer to expose the blocking pattern by the opening of the ion implantation mask pattern, and implanting impurity ions of a first conductivity type for forming a body region of the first conductivity type into the first region using the ion implantation mask pattern.Type: GrantFiled: February 14, 2019Date of Patent: July 28, 2020Assignee: SK hynix system ic Inc.Inventor: Soon Yeol Park
-
Patent number: 10608001Abstract: A nonvolatile memory device includes a plurality of unit cells. Each of the plurality of unit cells includes a first active region disposed in a substrate to extend in a first direction, a floating gate extending in a second direction to cross over the first active region, a first selection gate disposed to be adjacent to a first side surface of the floating gate to cross over the first active region, a second selection gate disposed to be adjacent to a second side surface of the floating gate opposite to the first selection gate to cross over the first active region, a first dielectric layer disposed between the floating gate and the first selection gate, and a second dielectric layer disposed between the floating gate and the second selection gate.Type: GrantFiled: December 6, 2018Date of Patent: March 31, 2020Assignee: SK hynix system ic Inc.Inventor: Kwang Il Choi
-
Patent number: 10217821Abstract: A power integrated device includes a channel region, a source region, a drift region, and a drain region. A stacked gate includes a gate insulation layer and a gate electrode. The stacked gate having a plurality of stacked gate extension portions that extend from the stacked gate to over the plurality of deep trench field insulation layers. A plurality of deep trench field insulation layers is disposed in the drift region. The deep trench field insulation layers are spaced apart from each other in a channel width direction. A height of the deep trench field insulation layers is greater than a width of the deep trench field insulation layer.Type: GrantFiled: April 27, 2016Date of Patent: February 26, 2019Assignee: SK HYNIX SYSTEM IC INC.Inventors: Joo Won Park, Sang Hyun Lee
-
Lateral high voltage integrated devices having trench insulation field plates and metal field plates
Patent number: 9852993Abstract: A high voltage integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region defined in the semiconductor layer and between the source region and the drift region, a trench insulation field plate disposed in the drift region, a recessed region provided in the trench isolation field plate, a metal field plate disposed over the trench insulation field plate, and filling the recessed region, a gate insulation layer provided over the channel region and extending over the drift region and over the trench insulation field plate, and a gate electrode disposed over the gate insulation layer.Type: GrantFiled: February 5, 2016Date of Patent: December 26, 2017Assignee: SK HYNIX SYSTEM IC INC.Inventor: Sung Kun Park -
Patent number: 9853146Abstract: A lateral double diffused MOS transistor including a substrate, a source region and a drain region disposed in the substrate, a first contact and a second contact connected to the source region and the drain region, respectively, a gate insulation layer and a gate electrode on the substrate, a first field plate extending from the gate electrode toward the drain region, a coupling gate disposed between the second contact and the first field plate on the substrate, the coupling gate having a coupling voltage by coupling operation with the second contact, and a second field plate disposed between the coupling gate and the first field plate on the substrate, the second field plate being electrically connected to the second field plate.Type: GrantFiled: March 28, 2016Date of Patent: December 26, 2017Assignee: SK hynix system ic Inc.Inventor: Sung Kun Park
-
Patent number: 9806160Abstract: A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region, a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending over the second drift region, a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insulaType: GrantFiled: August 15, 2016Date of Patent: October 31, 2017Assignee: SK HYNIX SYSTEM IC INC.Inventors: Dae Hoon Kim, Sang Hyun Lee
-
Patent number: 9799764Abstract: A lateral power integrated device includes a source region and a drain region disposed in a semiconductor layer and spaced apart from each other in a first direction, a drift region disposed in the semiconductor layer and surrounding the drain region, a channel region arranged between the source region and the drift region in the first direction, a plurality of planar insulation field plates disposed over the drift region and spaced apart from each other in a second direction, a plurality of trench insulation field plates disposed in the drift region, a gate insulation layer formed over the channel region, and a gate electrode formed over the gate insulation layer. Each of the trench insulation field plates is disposed between the planar insulation field plates in the second direction.Type: GrantFiled: June 3, 2016Date of Patent: October 24, 2017Assignee: SK HYNIX SYSTEM IC INC.Inventors: Joo Won Park, Kwang Sik Ko, Sang Hyun Lee