Abstract: An approach is proposed to support pin matching between different functional blocks in a circuit layout. A layout editing tool first presents functional blocks in the layout to a user and recognizes one or more user actions to identify a first boundary of a first/reference block and a second boundary of a second/target block among the functional blocks. The layout editing tool then identifies a first set of pins on the first boundary of the reference block and a second set of pins on the target block wherein each of the pins in the second set of pins belongs to a same net as at least one of the pins in the first set of pins. The second set of pins are sorted to be in the same order as the first set of pins based on their net ids and placed on the second boundary of the target block.

Abstract: A new approach is proposed to support layout objects selection and replication via a graphic-based layout editing tool running on a host. Specifically, the graphic-based layout editing tool presents a plurality of layout objects in a layout on a display of the host and enables a user to directionally and continuously move a cursor across the layout along a single line, wherein the single line intersects with and selects a starting group of one or more layout objects. The graphic-based layout editing tool then retrieves metadata and/or design rules associated with the starting group selected layout objects and to create an expanded group of layout objects by replicating and including one or more of the layout objects in the starting group selected layout objects. The graphic-based layout editing tool then presents the expanded group of layout objects on the display following the layout objects replication operation.