Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: A calibration circuit includes a pad suitable for receiving calibration data that toggles, a calibration reference voltage generation unit suitable for generating a calibration reference voltage from a median value of the calibration data, a comparison unit suitable for outputting a comparison signal by comparing the calibration reference voltage and a reference voltage with each other, and a reference voltage generation unit suitable for generating the reference voltage which is calibrated based on the comparison signal.