Abstract: A system and method for policing one or more flows of a data stream of packets associated with differing transmission protocols. The current capacity level for each flow is determined, as is the packet protocol associated with each packet. A packet parameter in the packet that is indicative of the bandwidth consumption of the packet is identified. The packet parameter is converted to a predetermined format if the packet is not associated with a predetermined packet protocol. A common bandwidth capacity test is performed to determine whether the packet is conforming or non-conforming, and is a function of the packet parameter and the current bandwidth capacity level.

Abstract: A multi-protocol, multi-stage, real-time frame classifier is disclosed. A preliminary multi-protocol frame composition analyzer is provided for performing preliminary multi-protocol frame classification for incoming frames. A parsing instruction generator is provided for processing at least the incoming frame and the preliminary multi-protocol frame classification to provide parsing instructions. A multi-stage parsing engine provides multi-stage parsing of the incoming frame according to the parsing instructions to generate search results presenting information about the incoming frame. An advanced level of data extraction is provided across various frame protocols without imposing a performance penalty. Longest prefix match searches and/or direct lookup searches are supported. Moreover, conditional extractions, instruction branching, multi-stage processing are all performed in real time.

Abstract: A fault tolerant, multi-protocol shelf management controller architecture that is extensible provides an intelligent platform management interface that is version indifferent as well as programmable and reconfigurable. The shelf management controller is arranged in a dual redundant configuration in a client-server mode and has a message driven configuration with the messages conforming to the Intelligent Platform Management Interface (IPMI) specification as extended by PICMG 3.0. In one embodiment, each shelf management controller includes at least one bit stream processor comprising sequenced stage machines implementing one or more finite state machines associated with one or more devices that are under control of the shelf management controller. The finite state machines could be hardware or software based. The shelf management controller is also modeled as a layered architecture that includes an IPMI API layer.

Abstract: A modular chassis arrangement for electronic modules that is configurable into a mechanically and electrically interconnected structure capable of delivering scalable mechanical, electrical and environmental functionality for a multiplicity of electronic modules. In one embodiment, the electronic modules are compliant with AdvancedTCA or MicroTCA standards in a modular Pico-Shelf configuration that support stackable and/or back-to-back multiple unit chassis.

Abstract: A system and method for policing one or more flows of a data stream of packets associated with differing transmission protocols. The current capacity level for each flow is determined, as is the packet protocol associated with each packet. A packet parameter in the packet that is indicative of the bandwidth consumption of the packet is identified. The packet parameter is converted to a predetermined format if the packet is not associated with a predetermined packet protocol. A common bandwidth capacity test is performed to determine whether the packet is conforming or non-conforming, and is a function of the packet parameter and the current bandwidth capacity level.

Abstract: Method and apparatus for sampling a high-speed digital signal include providing a data signal to a differential data input circuit, an offset control signal, and a strobe pulse. In response to the strobe pulse, the data signal is resolved into an output logic state based to a relatively greater extent on the differential data signal and to a relatively lesser extent on the offset control signal.

Abstract: A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.

Abstract: A system and method for policing individual flows and subflows of a data stream. Data traffic streams are classified into separate traffic flows, which in turn can be further classified into subflows, thereby providing for different priority levels of subsets of the flow. The subflows may be still further classified into additional subflows, creating a hierarchical, layered prioritization that can be metered at each vertical and horizontal level of the hierarchy. A packet flow rate of each of the subflows is compared to a predefined rate limit to allow subflows of a flow to have different priorities therebetween.

Abstract: A system and method for facilitating packet transformation of multi-protocol, multi-flow, streaming data. Packet portions subject to change are temporarily stored, and acted upon through processing of protocol-dependent instructions, resulting in a protocol-dependent modification of the temporarily stored packet information. Validity tags are associated with different segments of the temporarily-stored packet, where the state of each tag determines whether its corresponding packet segment will form part of the resulting modified packet. Only those packet segments identified as being part of the resulting modified packet are reassembled prior to dispatch of the packet.

Abstract: A phase control circuit includes a signal generator sub-circuit that generates a set of phase reference signals having phase angles generally distributed over a phase angle adjustment range. A controller sub-circuit produces weighting signals that assign relative priority for each of the phase reference signals, and includes at least one incremental adjustment input. The controller sub-circuit is adapted to maintain the weighting signals in a generally steady state when receiving signaling on the adjustment input that represents no adjustment, and to adjust relative intensities of the weighting signals based on stimulation of the adjustment input. The phase control circuit further includes a mixer sub-circuit that is coupled to the set of phase reference signals and to weighting signals that collectively control a mix of the phase reference signals. The mixer sub-circuit is adapted to produce an output signal having a phase angle that is based on the mix of the phase reference signals.

Abstract: A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data “eye” samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data “eye” samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.

Abstract: A system and method for facilitating packet transformation of multi-protocol, multi-flow, streaming data. Packet portions subject to change are temporarily stored, and acted upon through processing of protocol-dependent instructions, resulting in a protocol-dependent modification of the temporarily stored packet information. Validity tags are associated with different segments of the temporarily-stored packet, where the state of each tag determines whether its corresponding packet segment will form part of the resulting modified packet. Only those packet segments identified as being part of the resulting modified packet are reassembled prior to dispatch of the packet.

Abstract: A system and method for policing one or more flows of a data stream of packets associated with differing transmission protocols. The current capacity level for each flow is determined, as is the packet protocol associated with each packet. A packet parameter in the packet that is indicative of the bandwidth consumption of the packet is identified. The packet parameter is converted to a predetermined format if the packet is not associated with a predetermined packet protocol. A common bandwidth capacity test is performed to determine whether the packet is conforming or non-conforming, and is a function of the packet parameter and the current bandwidth capacity level.

Abstract: A circuit and method for controlling a slew rate of an output buffer. A pre-driver is provided that drives an input of an output pad driver of the output buffer. An output slew rate of the pre-driver is electronically selected among at least two electronically selectable slew rates. An output amplitude of the pre-driver is controlled such that the output amplitude is not greater than an amplitude that is generally minimally sufficient to cause the output pad driver to produce an output signal having a desired dynamic range.

Abstract: In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment.

Abstract: An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: In a multiprocessor system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. The system and method can reschedule processes to run on the processor on which the assignment is made.

Abstract: A delay locked loop (DLL) circuit that includes a delay line having a plurality of delay elements. Each delay element can be adapted to receive a clock input signal and generate a clock output signal, where the phase of each clock output signal is offset from the clock input signal. The delay line can be configured so that one clock input signal is a reference input clock signal and at least one clock output signal is a delay-line output clock signal. The feedback portion of the circuit can be configured to generate delay adjust signals based upon the phase offsets between pairs of clock signals. The delay adjust signals are fed back to the delay elements causing the reference input clock signal and the clock output signals to be phase-shifted apart equally about 360 degrees.

Abstract: A system and method initiates secure sessions without occupying a process on the server until the premaster key is received from the client.