Abstract: A method for determining a pixel output value of an imager; the imager having a plurality of pixels, a reset switch associated with each pixel and a select switch associated with each pixel; due to incident illumination upon a pixel of the imager after a reset period. The method captures a first pixel output value when the reset switch is OFF during a reset period and the select switch is ON during a reset period and captures a second pixel output value when the select switch is ON near an end of an integration period. If the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period preceding the first integration period and the select switch is ON during a reset period preceding the first integration period.

Abstract: An area is imaged with a non-standard aspect ratio, e.g. wide aspect ratio, digital imager to produce pixels of image data. At least a portion of the produced pixels of image data corresponding to the captured non-standard aspect ratio image is displayed beginning, for a given frame of pixels of image data, at a column of pixels of image data corresponding to a predetermined column of imaged pixels. The number of columns of display pixels is different than the number of columns of imaged pixels. Motion is detected in the imaged pixels so that a motion responsive portion of the imaged pixels corresponding to the captured non-standard aspect ratio image corresponding to a window of the imaged pixels having motion detected therein can be displayed.

Abstract: A circuit and method measure the output voltage of a CMOS pixel in a manner that substantially reduces all columnar pattern noise due to mismatches in the signal processing circuits including the correlated double sampling amplifiers and A/D converters. The circuit includes a test switch, operatively connected between a reference voltage source and a correlated double sampling amplifier, for applying a test voltage from the reference voltage source when the state of the test switch is ON to the correlated double sampling amplifier.

Abstract: A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor.

Abstract: There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels.

Abstract: There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels.