Abstract: Systems and methods for memory snapshots are disclosed. In particular, a memory device may include a volatile section and a backup persistent storage section. A snapshot manager circuit is positioned between a host control circuit or central processors. This snapshot manager circuit acts as a memory virtualization layer within the memory device and may use a redirect on write type command to put a snapshot of actively changed memory to a reserved memory area in the volatile section. A background function may copy the snapshots to the persistent storage section. Because the snapshot manager circuit is in the hardware memory access layers of the memory device, operation of the application is not interrupted or paused to access the specific memory sections. Further, snapshots are more readily available in the memory used by the host control circuit.

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

Abstract: A persistent memory unit for a computer system where the memory unit can detect a catastrophic event and automatically backup volatile memory into non-volatile memory. The memory unit can operate with a limited number of power inputs and detect the loss of power and then initiate a backup after the volatile memory of the memory unit has entered a stable self-refresh mode. The memory unit uses an on-board power management interface controller capable of redistributing power from an input power line and generating different power levels for different components on the memory unit.

Abstract: A deaggregated computing system having a memory centric computing storage controller can transfer data from a source to a destination node while dynamically updating a transfer route between them. The transfer route can be recalculated based on the current conditions of the routing nodes between the source and destination. Recalculating the transfer route can be based on power status, bandwidth, in-use status, current capacity, or failure conditions. The deaggregated computing system can include one or more processor units coupled to one or more storage and memory units all connected by the memory centric computing storage controller that can route control and data packets between the processor units and the storage and memory units. The processor units and the storage units can be connected by a combination of serial data communication links and a data storage fabric network.

Abstract: An memory management system with backup system, and a method of operation of a memory management system with backup system thereof, including: a memory module controller for detecting a power failure condition, the memory module controller including a nonvolatile memory controller; a compression controller integrated within the nonvolatile memory controller for receiving a data block from volatile memory; a compression engine within the compression controller for compressing the data block to form a compressed data block; and a sequencer for writing the compressed data block to nonvolatile memory.

Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.

Abstract: A data storage system, and a method of operation thereof, includes: a host initialization module for initializing a data storage unit; a command process module, coupled to the host initialization module, for processing a read command or a write command performed on the data storage unit; and a status scheduler module, coupled to the command process module, for generating a check status request to inquire a storage unit status of the data storage unit, wherein the check status request occurs without interrupting a host.

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.

Abstract: Approaches, techniques, and mechanisms are disclosed for a centralized backup power support system that improves testability of non-volatile dual in-line memory modules (NVDIMM) on Automatic Test Equipment (ATE) testers and in-system tests. An NVDIMM includes both volatile memories and non-volatile memories. According to an embodiment, a compact backup power distribution board is powered with an external power supply with an individual protection circuit. The backup power distribution board has an unlimited energy capacity for any density of NVDIMM and zero charge waiting time. According to an embodiment, instead of using an electric double-layer capacitor (EDLC) to support backup power, a resistor is used instead of an EDLC on each backup power module. There is no charging time when the backup power module does not have EDLC cells, resulting in significant reduction in test time and production cost and increase in production output.

Abstract: A memory management system, and method of operation thereof, includes: a primary device of a resilient storage module configured as a boot device for booting a computer system; an operational status received from the computer system; a secondary device of the resilient storage module configured as the boot device based on the operational status indicating a non-operational state; and a memory module controller of the resilient storage module for initiating a reboot operation using the secondary device as the boot device.

Abstract: A system and method of manufacture of an integrated circuit device system includes mounting a first elevated device on a first riser positioned adjacent to a base device. The first elevated device includes a first device overhang that extends over the base device. A second elevated device can be mounted on a second riser adjacent to the first riser to allow the attachment of a second elevated device mounted above the first elevated device to achieve higher component densities.

Abstract: Approaches, techniques, and mechanisms are disclosed for a test adapter designed to improve testability of non-volatile dual in-line memory modules (NVDIMM) on automatic test equipment (ATE) testers or in-system boards, which have inadequate power supplies. An NVDIMM includes both volatile memories and non-volatile memories. A test adapter is designed to supply increased power to an NVDIMM. A test adapter is implemented using an interposer or a printed circuit board (PCB) that may be inserted into a socket on an ATE tester or on an end-user system-level board. The interposer or PCB includes a power socket for attaching a power cable to supply the external power supply to the NVDIMM. A power on/off sequence is controlled by an ATE tester to simulate or test a system power on/off sequence. An external input power is always on, but both serial and backup power signals are only on during tests of an NVDIMM.

Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating portable module systems. The portable module systems can provide additional computing, memory, communication, networking, and power functionality in compact package that can be connected to a host system. The portable module system can dissipate thermal energy using an embedded cooling system to allow the use of high performance components. The portable module system can improve the functionality and computing capacity of the host system by linking off the shelf component boards with the external bus using a bridge interface unit to transfer information from an internal bus to the external bus.

Abstract: Approaches, techniques, and mechanisms are disclosed for a method of operation of a Flash-based block storage system including: transferring a first data to a logical block address; storing the first data in a physical block, of a storage array, associated with the logical block address; receiving a trim command for the logical block address; establishing a reserved physical block associated with the logical block address of the trim command; transferring second data for writing to the logical block address of the trim command; releasing the reserved physical block associated with the logical block address; and writing the second data to the logical block address.

Abstract: An interconnected memory system, and a method of operation thereof, including: a first discrete unit having a first unit processor and first unit memory module; a high-speed interconnect connected directly to the first unit memory module; and a second discrete unit having a second unit processor and a second unit memory module, the second unit memory module connected to the first unit memory module through the high-speed interconnect for utilizing the first unit memory module and the second unit memory module with the first unit processor.

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information.

Abstract: Approaches, techniques, and mechanisms are disclosed for improving data retention using a virtual timer. A memory controller may use a raw bit error rate (RBER) to find an equivalent temperature-accelerated data age of a data item. The data age is computed by using the initial RBER of virtual timing data (VTD) as a virtual write in time of the data item compared to a present time using the current RBER of the VTD. When the data age is determined to exceed a data retention threshold, a data refresh is performed on the data item at the memory block on the memory device. The data age may be stored as virtual timing data on the memory block.

Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.

Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.