Abstract: A digital image upscaling system enhances the visual quality of enlarged images by detecting diagonal edges and applying an appropriate scaling algorithm, such as a rotated bilinear scaling process, to output pixels associated with those edges. The rotated bilinear scaling process involves detecting diagonal edges and specifying a new frame of reference rotated 45° from the original frame of reference, and then selecting a rotated pixel set based on the new frame of reference. Bilinear interpolation in the new frame of reference using the rotated pixel set provides improved pixel data for the output pixel. Output pixels found not to be associated with diagonal edges are processed using standard bilinear interpolation.

Abstract: A method and system enhances the color of an image by manipulating the chrominance and/or luminance signals of the image. Specifically, a color enhancement system sharpens color changes for better picture quality on digital display systems. In one embodiment of the present invention, color changes are detected by a color change detection unit. If the color changes are significant, a color change sharpening unit sharpens the color change to enhance the image.

Abstract: An error diffusion system in accordance with an embodiment of the present invention adjusts the color depth of an RGB signal using error diffusion without the using an expensive frame buffer. Specifically, a color depth adjustment unit in accordance with the present invention can perform error diffusion on an RGB signal using two error buffers, which are smaller in memory size than typical line buffers that would be used for the video stream.

Abstract: A method and system of noise filtering is provided. The pixels of a first filter mask are separated into groups based on luminance . . . The sizes of each group is determined and a largest group is selected. The distance of each group of pixels from the largest group is also calculated. Pixels in groups that are small compared to the largest group and far from the largest group are tagged as noisy. After tagging the noisy pixels, additional filtering can be applied to the pixels of first filter mask without degradation from the tagged pixels.

Abstract: A method and circuit generates a complete picture from a series of digitized interlaced video fields. Each pixel in the complete picture is either duplicated from a digitized interlaced video field or interpolated from three adjoining digitized interlaced video fields. Interpolated pixels are computed from a combination of same-field and adjoining-field pixels. A percentage difference of the luminance values of the same-field and adjoining-field pixels included in the interpolation is used to maximize motion capture in the de-interlaced picture. Additional embodiments incorporate filtering of the percentage difference based on a threshold value to minimize soft noise in the de-interlaced picture.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention fine tune the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.