Abstract: A method and module for programmable power management and a system on chip are disclosed. The module includes: a token ring and an operation unit. The token ring is provided with a cyclically running token and forming a clock information. The operation unit is configured to perform a corresponding power management operation according to a predetermined operation step register and the token; wherein the step register records a time sequence for performing power management operations, the time sequence being represented by the clock information.

Abstract: A method for Bluetooth communication, a Bluetooth system and an electronic device are disclosed. The Bluetooth system includes: a data source device, a primary device and at least one secondary device. The primary device is configured to acquire, via Bluetooth communication, first data packets delivered by a data source device as a first data packet set and the secondary device is configured to acquire, via data interception, second data packets from the data source device as a second data packet set within at least a portion of a time period in the Bluetooth communication. The primary device communicates with the secondary device in a predetermined interaction node and sends the missing data packet from the first data packet set according to the details of acquisition of the data packets from the data interception.

Abstract: A QC-LDPC decoder includes: a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix; a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix; a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; and a check circuit, configured to determine whether the variable message satisfies a check standard or not.

Abstract: A method for Bluetooth communication includes: in Bluetooth communication, allocating bandwidth resources as a first bandwidth resource for communication with a data source device and a second bandwidth resource for communication with a slave device; in the communication with the data source device, receiving and caching data from the data source device; in the communication with the slave device, determining whether the volume of the cached data is less than a first threshold; and if the data volume of the cached data is less than the first threshold, using at least a portion of the second bandwidth resource for the communication with the data source device.

Abstract: A method includes: sending a Real-time Transport Protocol data packet to a client; receiving a bandwidth value and a frame rate value fed back by the client, the bandwidth value and the frame rate value being calculated by parsing the data packet; obtaining a corresponding bandwidth weight according to the bandwidth value, and obtaining a corresponding frame rate weight according to the frame rate value; obtaining a quantization table weight according to the bandwidth weight and the frame rate weight; and matching image transmission data according to the quantization table weight; ands ending matched image data to the client.

Abstract: A method for Bluetooth mode switching, a Bluetooth system and an electronic device are disclosed. The module includes: in a data listen mode, determining, according to transmission of data packets, whether a predetermined switching condition is satisfied, wherein the data listen mode is a working mode that allows unidirectional acquisition of data packets delivered by a data source device in a Bluetooth communication process; and if the predetermined switching condition is satisfied, requesting to establish Bluetooth communication with the data source device, and switching to a Bluetooth communication mode.

Abstract: A method for switching Bluetooth working modes, an electronic device, and a Bluetooth chip are disclosed. The method includes: executing a first Bluetooth working mode, the first Bluetooth working mode including a working state in which data is normally transmitted and an error state in which data fails to be transmitted; monitoring a first interrupt request signal sent in a second Bluetooth working mode if the first Bluetooth working mode works in the working state; and executing the second Bluetooth working mode and enabling the first Bluetooth working mode to work in the error state if the first interrupt request signal is present.

Abstract: A method and a system for Bluetooth communication, and an electronic device are disclosed. The method includes: acquiring data packets from a data source device by means of data interception within at least a portion of a time period in a Bluetooth communication process, wherein the data interception is a working mode that allows unidirectional acquisition of data packets delivered by the data source device in the Bluetooth communication process.

Abstract: A method for forwarding Bluetooth data, an electronic device, a Bluetooth device, and a Bluetooth system are disclosed. The method includes: in a Bluetooth communication process, receiving source data from a data output device as cached data, and forwarding the source data; and preferentially allocating a Bluetooth communication bandwidth to receive the source data if a data volume of the cached data is less than a first predetermined threshold; or preferentially allocating a Bluetooth communication bandwidth to forward the source data if a data volume of to-be-forwarded source data is greater than a second predetermined threshold.

Abstract: A mobile communication device includes a first antenna configured to transmit and receive RF signals, a first capacitive sensor adjacent to the first antenna, a second antenna configured to transmit and receive RF signals, a second capacitive sensor adjacent to the second antenna, a sensing circuit in communication with the first capacitive sensor and the second capacitive sensor, the sensing circuit being that can determine the position of a user's hand adjacent to the first antenna or the second antenna in response to sensing signals received from the first capacitive sensor and the second capacitive sensor, and an antenna switching circuit that can select the first antenna or the second antenna to transmit and receive RF signals to enable wireless communications in response to the position of the user' hand relative to the first antenna and the second antenna as determined by the sensing circuit.

Abstract: A computer system for software development and debugging for an embedded system includes a Universal Serial Bus (USB), a host computer comprising a USB driver interfaced with the USB, wherein the USB driver can multiplex application data and debug data to and from the USB, and an embedded system comprising a USB module interfaced with the USB. The USB module can multiplex the application data and the debug data to and from the host computer via the USB.

Abstract: A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.

Abstract: An electrostatic discharge protection circuit for an electronic device includes an output buffer including a transistor having a gate configured to receive a control signal, a source connected to a voltage supply terminal, and a drain connected to a pad; and an ESD trigger circuit configured to produce a first electronic signal in response to an electrostatic voltage between the pad or the voltage supply terminal. The first electronic signal can isolate the control signal from the gate of the transistor and to turn on the transistor to discharge the electrostatic voltage between the pad and the voltage supply terminal.

Abstract: A bandgap voltage reference circuit includes a bandgap voltage generation circuit that can produce a bandgap reference voltage in response to an activation voltage signal, a start-up circuit that can produce the activation voltage signal in response to one-shot voltage pulse and an one-shot pulse generator circuit configured to produce the one-shot voltage pulse. The start-up circuit can be automatically shut off after the one-shot voltage pulse.

Abstract: An electrostatic discharge protection circuit includes a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal (VDD) and an input pad (PAD), a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal (VSS), a first capacitor connected between VDD and a node VT that is connected to gate terminals of the second NMOS transistor and the third NMOS transistor, a second capacitor connected between the node VT and PAD, and a diode connected between VDD and the node VT.

Abstract: An electrostatic discharge protection circuit includes a high-voltage supply terminal (VDD), an input/output (IO) pad, and a first shunting transistor that can discharge electrostatic charges between the IO pad and VDD in response to a control signal. A trigger circuit can output the control signal in response to an electrostatic voltage between the IO pad and VDD. The electrostatic discharge protection circuit also includes a first group of serially connected diodes, which includes a first end connected to the IO pad and a second end configured to supply power to the trigger circuit.

Abstract: A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.

Abstract: A voltage controlled oscillator includes a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN, a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP, a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor. A first PMOS transistor includes a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN. A second PMOS transistor includes a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP.

Abstract: An output buffer having slew-rate control and crossbar current control includes a pull-up PMOS transistor, a pull-down NMOS transistor, a pull-up network coupled to the gate of the pull-up PMOS transistor, and a pull-down network coupled to the gate of the pull-down NMOS transistor.

Abstract: An oscillator circuit includes a current source comprising an amplifier, a first resistor, a second resistor, and a third inverter whose input and output are connected and coupled with an input of the amplifier. The amplifier is configured to generate a first current flowing through the first resistor and the second resistor.