Patents Assigned to SMSC Holdings SARL
  • Patent number: 9723314
    Abstract: A system, circuit and method are provided herein for reducing perceived flicker in video images transmitted using compression and bit rate control. According to one embodiment of the method, a parameter used in the video compression scheme is stored. The parameter stored is one that is subject to adjustment during normal operation of the video compression scheme. Compressed video frame data issued by a compression encoder is used to test for a still-picture condition. When a still-picture condition is detected, the value of the parameter used by the video compression scheme is fixed to the stored value for the duration of the still-picture condition. An embodiment of the system includes an encoder, buffer, bit rate controller, and flicker reduction circuit. An embodiment of the flicker reduction circuit includes a still-picture detection circuit operably coupled to a compressed data path beginning at the output of the encoder.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 1, 2017
    Assignee: SMSC Holdings SARL
    Inventors: Santosh Shetty, Shih-chung Chao
  • Publication number: 20130318205
    Abstract: An emulation device is used to stream media content from a digital media server to a digital media renderer. The emulation system receives a pulse code modulation data stream from the digital media server via a network interface, and stores the data in a buffer. The emulation system is attachable to the digital media renderer, and is recognized as a storage device containing an emulated media file. When the digital media renderer plays the emulated media file, the emulation device reads the PCM data from the buffer to use as sound or video data of the emulated media file.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: SMSC HOLDINGS SARL.
    Inventors: Vadivelu N, Satishkumar Ramaraj, Hari Bojan
  • Publication number: 20130297829
    Abstract: The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 7, 2013
    Applicant: SMSC Holdings Sarl.
    Inventors: Alan Berenbaum, Eileen Marando, Richard Wahler
  • Publication number: 20130223515
    Abstract: A system, circuit and method are provided herein for reducing perceived flicker in video images transmitted using compression and bit rate control. According to one embodiment of the method, a parameter used in the video compression scheme is stored. The parameter stored is one that is subject to adjustment during normal operation of the video compression scheme. Compressed video frame data issued by a compression encoder is used to test for a still-picture condition. When a still-picture condition is detected, the value of the parameter used by the video compression scheme is fixed to the stored value for the duration of the still-picture condition. An embodiment of the system includes an encoder, buffer, bit rate controller, and flicker reduction circuit. An embodiment of the flicker reduction circuit includes a still-picture detection circuit operably coupled to a compressed data path beginning at the output of the encoder.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: SMSC HOLDINGS SARL
    Inventors: Santosh Shetty, Shih-chung Chao
  • Patent number: 7711078
    Abstract: Systems and methods related to digital frequency locked looping to synchronize frequencies between the local signal from a local oscillator and a reference clock signal from a remote oscillator. A reference counter increments its count for every pulse in the reference clock signal. The value in the reference counter is compared to a configurable reference value. Whenever a match between the reference counter value and the reference value occurs, a hit signal is generated and the reference counter value is reinitialized. Concurrent with the above, a feedback counter increments for every pulse from the local signal. When the hit signal is generated, the value in the feedback counter is compared to a configurable feedback value (by subtraction) to generate a difference value. The difference value is then converted to a frequency adjust signal for use in either increasing or decreasing the frequency of the local oscillator. The hit signal also reinitializes the feedback counter.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 4, 2010
    Assignee: SMSC Holdings SARL
    Inventors: Jean-Paul DeCruyenaere, Ralph Mason, Anita Netherton