Abstract: A circuit arrangement for connecting a plurality of digitally operated terminals to a single communications circuit of a master digital processing unit, such as a central computer, for transmission of information therebetween. The circuit comprises a first data bus for delivery of information from the processing unit to the terminals and a second data bus for delivery of information from each of the individual terminals to the central processing unit. A connecting circuit connects each of the individual terminals to the buses in a series arrangement such that each of the terminals are serially connected to the central computer through the single central port thereof.