Abstract: A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock signal; a dual path filter for receiving the phase detector output signal, the dual path filter including a first path for generating a digital proportional output signal that is proportional to the phase detector output signal and a second path having an integral digital filter for generating a digital integral output signal that is proportional to an integral of the phase detector output signal; and a digitally controlled oscillator for receiving the proportional output signal and the integral output signal as tuning inputs and generating in dependence thereon an output clock signal from which the feedback clock signal is obtained. The circuit can be implemented in a receive path of a serializer/deserializer.

Abstract: An analog digital converter with switched-capacitor reset architecture. The analog to digital converter (ADC) includes a plurality of pipelined stages, each stage including an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC). The MDAC includes an opamp and a reset circuit connected to inputs of the opamp, the reset circuit including first and second capacitors and switching circuitry for precharging each of the first and second capacitors to a difference between the input and output common-mode voltages of the opamp, and during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.

Abstract: A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide fine frequency resolution in addition to randomization and noise shaping of fractional quantization noise. The delta-sigma modulator is clocked at rates higher than the synthesizer reference clock resulting in an improvement in clock jitter at the output of the frequency synthesizer. A glitch-free phase multiplexer design is used to implement the phase rotator fractional divider to enables operation at rates higher than the reference clock. The over-sampling ratio of the delta-sigma modulator over the reference clock frequency of the PLL translates directly into an improvement in the quality of the output clock with respect to fractional quantization noise, phase mismatch, and digital noise injection.

Abstract: A duty-cycle correction (DCC) circuit adapted to adjust the duty cycle of a differential clock signal to conform it to the requirements of a half-rate clocking system. In a representative embodiment, the DCC circuit has a buffer circuit adapted to generate a differential output clock signal by adding offset voltage to a differential input clock signal. A feedback loop coupled to the buffer circuit processes the output clock signal to evaluate deviation of its duty-cycle value from 50% and, based on the evaluation, configures the buffer circuit to adjust the offset voltage such that the duty-cycle deviation is reduced. The feedback loop and the buffer circuit are controlled by a duty-cycle calibration engine, e.g., a digital logic circuit adapted to determine an appropriate value for the offset voltage, which causes the duty-cycle value in the output clock signal to be substantially 50% regardless of the duty-cycle value in the input clock signal.

Abstract: A fractional-N frequency synthesizer is described that includes a voltage controlled oscillator (VCO), a programmable integer divider, and a glitch-free phase rotator. The phase select inputs of the phase rotator are controlled by a delta-sigma modulator to provide fine frequency resolution in addition to randomization and noise shaping of fractional quantization noise. The delta-sigma modulator is clocked at rates higher than the synthesizer reference clock resulting in an improvement in clock jitter at the output of the frequency synthesizer. A glitch-free phase multiplexer design is used to implement the phase rotator fractional divider to enables operation at rates higher than the reference clock. The over-sampling ratio of the delta-sigma modulator over the reference clock frequency of the PLL translates directly into an improvement in the quality of the output clock with respect to fractional quantization noise, phase mismatch, and digital noise injection.