Patents Assigned to Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux
  • Patent number: 5457338
    Abstract: A process for manufacturing isolated semi conductor components in a semi conductor wafer of the type used in bipolar technology. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer at the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: October 10, 1995
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux E.F.C.I.S.
    Inventor: Joseph Borel
  • Patent number: 4805759
    Abstract: In an installation for conveying delicate objects such as semiconductor layers during processing operations and for handling such objects in a controlled atmosphere, wheeled carriages are drawn along tracks by an endless belt and are not driven by motors in order to satisfy conditions of cleanliness and freedom from pollution hazards. By means of transfer tools, object-holding cassettes are taken from the carriages during operation and replaced on the carriages after processing in the different machines.
    Type: Grant
    Filed: December 8, 1986
    Date of Patent: February 21, 1989
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux EFCIS
    Inventors: Andre Rochet, Guy Dubois, Louis Faure, Alain Lalanne
  • Patent number: 4780429
    Abstract: In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.
    Type: Grant
    Filed: January 12, 1987
    Date of Patent: October 25, 1988
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux Efcis
    Inventors: Alain Roche, Joseph Borel, Annie Baudrant
  • Patent number: 4721865
    Abstract: The invention relates to a detector of the mean level of a signal particularly intended to indicate whether an expected alternating signal is absent or present. This detector uses an analog comparator, a digital counter and a converter for establishing an analog signal to be compared with the expected rectified signal. The counter content oscillates round the mean value of the rectified signal. The counter serves as a digital integrator for the sign of the difference between the input signal and the content of the counter, in such a way that on average the input signal is just as often above as below the counter content. The digital - analog conversion can take place with the aid of switched capacitors.
    Type: Grant
    Filed: September 18, 1985
    Date of Patent: January 26, 1988
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux - Efcis
    Inventors: Louis Tallaron, Jean C. Bertails
  • Patent number: 4706209
    Abstract: The invention concerns the overflow test circuit of an arithmetic and logic unit. The circuit described does not require receiving an indication on the operating in addition or subtraction of the ALU; it receives simply the carrying input the carrying and the result output of the cell of the highest rank of the ALU: and it supplies a positive overflow signal or a negative overflow signal, when the result of the addition or subtraction of two numbers exceeds the capacity of the ALU. Two gates with three inputs and three inverters are sufficient to establish the overflow test circuit.
    Type: Grant
    Filed: January 31, 1985
    Date of Patent: November 10, 1987
    Assignee: Societe pour l'Etude et la Fabrication de Circuit Integres Speciaux-E.F.C.I.S.
    Inventor: Andre Picco
  • Patent number: 4679309
    Abstract: A process for manufacturing isolated semi conductor components in a semi conductor wafer of the type used in bipolar technology. In this process, polycrystalline silicon is deposited in a recess in a silicon substrate whose walls are insulated by a silicon nitride layer except for an opening formed in this nitride layer at the bottom of said recess. Then, the polycrystalline silicon is re-epitaxied so as to become monocrystalline silicon by thermal heating from the "nucleus" formed by the underlying silicon in said opening.
    Type: Grant
    Filed: June 18, 1984
    Date of Patent: July 14, 1987
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux E.F.C.I.S.
    Inventor: Joseph Borel
  • Patent number: 4651036
    Abstract: A data transfer bus preloading circuit including a large sized transistor r ensuring rapid bus conductor preloading. This transistor is conductive at the beginning of the preloading step proper, but is blocked as the bus voltage reaches the desired preload value which corresponds to the sum of the respective threshold voltages of two other transistors of the circuit. The circuit includes five field effect transistors, two supply terminals, a preloading control input terminal and a preloading inhibiting input terminal. The large size transistor is connected between a first supply terminal and the output terminal of the circuit. A second transistor is connected between the gates of the first and third transistors. The gate of the second transistor is connected to the preloading control input terminal. The third transistor is connected between the source terminal and the fifth transistor. The gate and source of the third transistor are connected together.
    Type: Grant
    Filed: February 21, 1985
    Date of Patent: March 17, 1987
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux
    Inventor: Louis Tallaron
  • Patent number: 4628472
    Abstract: The invention provides a high-speed binary multiplier.The binary digits x.sub.i of the multiplicand X and y.sub.j of the multiplier Y (in two complement form) are converted by respective coders into coefficients a.sub.i and b.sub.j such thatX=a.sub.m-1 2.sup.m-1 + . . . a.sub.1 2.sup.1 +a.sub.oY=b.sub.n-1 2.sup.n-1 + . . . b.sub.1 2.sup.1 +b.sub.owhere a.sub.i and b.sub.j can only assume three values 0,1 or -1 and where two consecutive coefficients a.sub.i and a.sub.i-1 and b.sub.j or b.sub.j-1 cannot both be non zero. a.sub.i and b.sub.j are each represented by a pair of binary logic signals (r.sub.i,u.sub.i) or (s.sub.j,v.sub.j). The signals (s.sub.j,v.sub.j) serve for controlling a routing circuit which further receives as signals to be routed the signals (r.sub.i,u.sub.i) for directing these signals, depending on the values of coefficients b.sub.j, to the appropriate inputs of an adder stage operating without carry-over propagation. The outputs of this adder are reconverted into binary form by a decoder.
    Type: Grant
    Filed: November 18, 1983
    Date of Patent: December 9, 1986
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux-Efcis.sup.2
    Inventor: Thierry Fensch
  • Patent number: 4599575
    Abstract: In order to diminish the risk of oscillation of a broad-band amplifier 20 MHz without considerably reducing the product gain x bandwidth, this amplifier comprises a differential stage T1, T2, T3, T4, a follower stage T5, T6, two common mode feed-back braches T8, T9, T5 on the one hand, T11, T12, T10, on the other hand, and compensation capacitors C1, C2 that are unbalanced, C2 higher than C1, between the supply terminal B and each of the outputs S1, S2 of the differential stage.
    Type: Grant
    Filed: April 3, 1985
    Date of Patent: July 8, 1986
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux Efcis
    Inventor: Patrick Bernard
  • Patent number: 4595999
    Abstract: The invention relates to a non-volatile static memory cell.The cell comprises a bistable flip-flop with four transistors, with two complementary outputs. Between the outputs is placed a non-volatile storage element comprising two complementary transistors in series, namely a p channel transistor and a n channel transistor, said transistors having a common floating grid and a common control grid. A charge injection zone is provided on the side of the source region on the n channel transistor. The region is connected to an output of the flip-flop, while the control grid is connected to the other output.Repositioning takes place without any reversal of the original state of the flip-flop.
    Type: Grant
    Filed: March 29, 1984
    Date of Patent: June 17, 1986
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux
    Inventor: Michel Betirac
  • Patent number: 4575708
    Abstract: Being given the number among P of a data, an attempt is made to find the number among N of said data in a group of N data incorporating P selected data. The sequence numbers of these P data appear in a register having N locations and the sequence number of the chosen data among P appears in a second register with P locations. The locations of the second register are connected to the rows of a switching circuit, each of these rows having N cells, which connect the input of one cell to the following cell of the same rank or to the following cell of the lower rank, as a function of the content of the corresponding location of the first register. Thus, at the outputs of the columns there are signals, whereof only one is at a level different from the others and corresponding to the number j among N of the chosen data.
    Type: Grant
    Filed: March 20, 1984
    Date of Patent: March 11, 1986
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux E.F.C.I.S.
    Inventor: Jacques Meyer
  • Patent number: 4561932
    Abstract: A method for manufacturing integrated circuits is provided in which monocrystalline silicon islets are formed completely isolated from the substrate itself made from monocrystalline silicon, by a thick oxide layer.This thick oxide layer is formed in the following way: silicon islets are formed whose top and sides are protected with silicon nitride. Then the silicon is etched isotropically, which hollows out deeply under the islets. Thick oxidization then makes up the whole of the silicon under the islets.Thus isolated silicon islets are obtained of the same crystalline quality as the substrate.
    Type: Grant
    Filed: November 2, 1984
    Date of Patent: December 31, 1985
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux E.F.C.I.S.
    Inventors: Yvon Gris, Agustin Monroy
  • Patent number: 4541073
    Abstract: A flip-flop further comprising two branches with MNOS elements serially connected with P channel MOS transistors for permitting a non-volatile storing of the informations comprised in the flip-flop at a chosen storing time. The memorization of the state of the flip-flop can be made in a single cycle by acting on the control signal applied to the gate of the P channel transistors and on the supply voltage of the device. In the same way, the resetting can be made in a single cycle.
    Type: Grant
    Filed: September 28, 1982
    Date of Patent: September 10, 1985
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux
    Inventors: Jean-Michel Brice, Patrick Maillart
  • Patent number: 4513265
    Abstract: A circuit having an inductive characteristic for the realization of filters in integrated circuits is constructed solely from switched capacitors and an operational amplifier. The circuit is provided between a first and a second terminal with a first capacitor in series with at least one switch. The switch is capable either of connecting the first capacitor between said two terminals or of isolating said capacitor from the first terminal. The circuit further comprises an operational amplifier having a feedback path between its output and its input via a second capacitor, and additional switches for transferring charges from the input of the circuit to the first capacitor and then from the first capacitor to the second capacitor, then again from the second capacitor to the first capacitor. Under these conditions, the circuit exhibits the characteristics of an inductance.
    Type: Grant
    Filed: September 24, 1982
    Date of Patent: April 23, 1985
    Assignee: Societe Pour L'Etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S.
    Inventor: Boris Sokoloff
  • Patent number: 4459542
    Abstract: A spectrum analyzer comprises a plurality of filters each provided with a low-pass output and a high-pass output both having the same cutoff frequency which is different in the case of the different filters. Switching means are provided for periodically connecting pairs of filters in cascade during a first time interval between one input for signals to be analyzed and a filtered-signal transmission channel assigned to each pair of filters. One of the filters of each pair has a high-pass (or respectively low-pass) output connected to the input of the other filter whose utilization output is the low-pass (or respectively high-pass) output. The switching means also have the function of periodically establishing a cascade connection during a second time interval between pairs of filters which are different from the first pairs. In the case of one filter, the output utilized during the second time interval is different from the output utilized during the first time interval.
    Type: Grant
    Filed: July 9, 1982
    Date of Patent: July 10, 1984
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux-EFCIS
    Inventors: Christian Terrier, Christian Caillon, Daniel Barbier, deceased
  • Patent number: 4451328
    Abstract: A process for manufacturing high-resistance elements for integrated circuits, in which the resistors are positioned on a layer of silica covering an integrated circuit, in a polycrystalline silicon zone possessing high resistivity, current supply lines being formed of a layer of polycrystalline silicon possessing low resistivity, surmounted by a layer of tantalum silicide. Plugs of photosensitive resin, deposited on a layer of polycrystalline silicon, are used to mark out a zone where the resistor is to be positioned, from zones in which resistivity is reduced by doping, and also to "lift-off" the layer of tantalum silicide on top of the resistor position.
    Type: Grant
    Filed: September 27, 1982
    Date of Patent: May 29, 1984
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux - E.F.C.I.S.
    Inventor: Guy Dubois
  • Patent number: 4442398
    Abstract: An integrated circuit constituting a current generator formed by CMOS technology comprises a first pair of similar transistors, one of which recopies the current of the other, subject to a proportionality factor; a second pair of similar transistors, one of which recopies the source voltage of the other; a third pair of similar transistors having different threshold voltages in contrast to the other pairs. A resistor is placed in series with one of the transistors of the third pair in order to compensate for the difference between the threshold voltages, an additional transistor being provided for recopying the current in one of the transistors aforementioned. The current thus produced is stable in time as well as independent of temperature and of the circuit supply voltage.
    Type: Grant
    Filed: November 9, 1981
    Date of Patent: April 10, 1984
    Assignee: Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux-E.F.C.I.S.
    Inventors: Jean-Claude Bertails, Christian Perrin
  • Patent number: 4356055
    Abstract: A process and device for plasma etching a thin layer. The process includes the steps of identifying a plateau in gas pressure that occurs slightly before the end of etching and then detecting a pressure variation (increase or decrease) from the plateau pressure. Etching is stopped at a predetermined time interval after the variation following the plateau begins. The device includes one or more pressure sensors and means for determining the plateau and subsequent pressure variation.
    Type: Grant
    Filed: July 22, 1981
    Date of Patent: October 26, 1982
    Assignee: Societe pour L'Etude et la Fabrication de Circuits Integres Speciaux EFCIS
    Inventor: Michel Montier
  • Patent number: 4110762
    Abstract: A machine for drawing on a photographic plate and especially for integrated ircuit masks comprises an electro-optical imager having an optical axis x-x', means for controlling the optical state of each point which has dimensions corresponding to the smallest detail to be drawn on the plate, the entire light beam issuing from the imager being applied to an objective which provides a magnification n and has an axis corresponding to the optic axis. Means for producing the relative displacement of the imager and of the photosensitive plate in a plane at right angles to the optic axis and in two orthogonal directions are controlled as a function of indications supplied by means for measuring the relative displacement.
    Type: Grant
    Filed: June 6, 1977
    Date of Patent: August 29, 1978
    Assignees: Commissariat a l'Energie Atomique, Societe pour l'Etude et la Fabrication de Circuits Integres Speciaux
    Inventor: Paul Tigreat