Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

Abstract: In one aspect, an information processing apparatus includes a first acquisition module, a first extraction module, a first generation module, a second extraction module, a derivation module, and a first output control module. The first acquisition module acquires an input image to output a first image and a second image. The first extraction module extracts first characteristic point information from the first image. The first generation module generates a third image obtained by reducing a data amount of the second image. The second extraction module extracts second characteristic point information from the third image. The derivation module derives a difference between the first characteristic point information and the second characteristic point information. The first output control module outputs the third image corrected in accordance with the difference as an output image.

Abstract: The voltage hold circuit is a voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit including: a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every the processing cycle.

Abstract: An information transmission method of a mobile reception terminal that is capable of connecting to a server over a network and capable of receiving a direct wave and a reflected wave of radio waves transmitted by a transmission station that has a fixed position and transmits radio waves of a same modulation scheme continuously or periodically, includes: creating a delay profile of reception of the direct wave and the reflected wave that indicates a time difference between the direct wave and the reflected wave; and transmitting the delay profile to the server over the network.

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

Abstract: A semiconductor device includes a first wiring; a first circuit region provided with a first power supply wiring and a first ground wiring; a second circuit region provided with a second power supply wiring and a second ground wiring; and a bidirectional diode connected between the first and second ground wirings, and provided with first and second diodes. The first diode includes a first impurity region of a first conductive type, connected to the second ground wiring, and a second impurity region of a second conductive type, connected to the first ground wiring. The second diode includes a third impurity region of the second conductive type connected to the second ground wiring, and a fourth impurity region of the first conductive type connected to the first ground wiring. Any of the first to fourth impurity regions, or any combination of the impurity regions is connected to the first wiring.

Abstract: In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: Differential attenuation circuitry, including: first and second input nodes; first and second output nodes; and an impedance network connected between the first and second input nodes and the first and second output nodes to provide a differential output voltage signal between the first and second output nodes which is attenuated compared to a differential input voltage signal applied between the first and second input nodes, wherein the impedance network includes: a common-mode node; a first impedance network connected between the first input node, the common-mode node and the first output node; and a second impedance network connected between the second input node, the common-mode node and the second output node, and wherein the differential attenuation circuitry further includes: an input-to-input path comprising one or more impedances and one or more switches connected between the first and second input nodes to provide a current path independent of the common-mode node.

Abstract: An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.

Abstract: The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

Abstract: An analog-to-digital converter circuit includes: a reference voltage node configured to be supplied with a reference voltage; an analog-to-digital converter circuit unit including a reference voltage input node configured to be electrically connected to the reference voltage node, the reference voltage being input to the reference voltage input node, the analog-to-digital converter circuit unit configured to convert an input analog voltage into a digital value based on the reference voltage; a voltage generation circuit configured to be electrically connected to the reference voltage node and generate an internal operating voltage based on the reference voltage; and a charge compensation circuit configured to operate based on the internal operating voltage, and during operation of the analog-to-digital converter circuit unit, the charge compensation circuit configured to compensate the reference voltage input node for charge.

Abstract: A semiconductor device includes a substrate; a first transistor formed over the substrate; a second transistor formed over the first transistor; a third transistor formed over the substrate; and a fourth transistor formed over the third transistor. The first, second, third, and fourth transistor include first, second, third, and fourth gate electrodes, respectively, and include first, second, third, and fourth source regions and first, second, third, and fourth drain region of first, second, third, and fourth conductivity types, respectively. The first conductivity type is different from the second conductivity type. The third conductivity type is the same as the fourth conductivity type. The first and second gate electrodes are integrated, and the third and fourth gate electrode are integrated.

Abstract: A control device that executes a local dimming process of a display, the control device, includes a memory; and a processor configured to execute a process including identifying a changed area in which an image is changed in a frame to be displayed on the display, analyzing, in a case where the changed area is identified, every time a frame to be displayed on the display is received, the image in the changed area in the received frame, in a corresponding one of first units for processing so that the image in the changed area is analyzed in the first units for processing over multiple frames by time division processing, and generating control information for controlling the local dimming process for a corresponding area on the display, every time an analysis result with respect to the image in the first unit of processing is output.

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

Abstract: An image processing device for performing correction processing on original image data generated by an image-capturing element configured to receive light with a plurality of pixels through a color filter including segments of a red color and at least one complementary color includes a processing circuitry being configured to perform operations including converting the original image data into primary color-based image data represented in a primary color-based color space, acquiring a statistical value of a plurality of pieces of pixel data corresponding to the plurality of pixels from the primary color-based image data, calculating a correction parameter by using the statistical value, and correcting the original image data based on the correction parameter.

Abstract: In a p-type region, a nanosheet farthest from an n-type region has a face exposed from a first gate interconnect on the side away from the n-type region in the Y direction. In the n-type region, a nanosheet farthest from the p-type region has a face exposed from a second gate interconnect on the side away from the p-type region in the Y direction. In the p-type region, a nanosheet closest to the n-type region has a face exposed from the first gate interconnect on the side closer to the n-type region in the Y direction. In the n-type region, a nanosheet closest to the p-type region has a face exposed from the second gate interconnect on the side closer to the p-type region in the Y direction.

Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.

Abstract: Nanosheets 21a to 21d are formed in line in this order in the X direction, and nanosheets 21e to 21h are formed in line in this order in the X direction. Faces of the nanosheets 21c, 21f, and 21g on the first side as one of the opposite sides in the X direction are exposed from gate interconnects 31c, 31e, and 31f, respectively. Faces of the nanosheets 21a, 21b, 21d, 21e, and 21h on the second side as the other side in the X direction are exposed from gate interconnects 31a to 31d and 31g, respectively.