Abstract: A memory circuit includes memory groups each of which includes memory cells, and is configured to execute a write operation or a read operation in response to a request signal; memory group controllers each of which is provided for a corresponding one of the memory groups; and a first memory controller configured to output a request signal received from an outside to an adjacent memory group controller, wherein, in a case where an address signal included in the received request signal indicates the corresponding one of the memory groups, said each of the memory group controllers outputs the request signal to the corresponding one of the memory groups, and in a case where the address signal indicates a memory group other than the corresponding one of the memory groups, outputs the request signal to a memory group controller at a succeeding stage.

Abstract: An output circuit outputs an output signal having an amplitude VCCH responsive to an input signal having an amplitude VCCL. The output circuit includes: first and second p-type transistors connected in series between VCCH and an output terminal; a first n-type transistor grounded at its source and receiving a first signal at its gate; a third p-type transistor connected to VCCH at its source, connected to the gate of the first p-type transistor at its drain, and receiving a second signal at its gate; and a first diode connected between the drains of the first n-type transistor and the third p-type transistor.

Abstract: An image processing apparatus performs a process including acquiring first image data, calculating a white balance value used for an automatic white balance adjustment according to the first image data, performing an automatic white balance adjustment on the first image data according to the white balance value to generate image data after a first correction, calculating a first luminance in the image data after the first correction by adding a color difference component to a luminance, and detecting a first region including a pixel having the first luminance higher than a first threshold value, calculating a correction degree of color information of a pixel included in the first region in the image data after the first correction, according to the first luminance, and correcting the color information of the pixel included in the first region in the image data after the first correction, according to the correction degree.

Abstract: According to one embodiment, an information processing device includes: a first determination module that determines first information concerning deformation of a projection surface on which a peripheral image of a moving body is projected; and a deformation module that deforms the projection surface based on the first information. The first determination module includes an information retaining module that accumulates second information in the past used for determining the first information, and determines the first information based on the second information in the past at an operation start time of the moving body.

Abstract: A loop filter includes: an input terminal and an output terminal mutually connected via a first node; a filter unit; and a low pass filter provided between a second power supply terminal and a third power supply node. One or more of at least one first resistive element and at least one first capacitive element constituting the filter unit are provided between the first node and a first power supply terminal via a switch part, and at least either the resistance value or the capacitance value of the filter unit is variable with on/off of the switch part. The switch part is constituted by transistors, and the backgate of at least one of the transistors is connected to the third power supply node.

Abstract: An AD converter device includes: a plurality of AD converter circuit units which performs analog-to-digital conversion in a time-interleaved manner; and a multiplexer circuit which generates a digital signal from output signals of the AD converter circuit units. The multiplexer circuit includes logic circuits and intermediate connection wirings placed to be distributed in the AD converter circuit units, the logic circuits are connected in a tournament configuration. In each of the AD converter circuit units, an output circuit and a first element circuit part including the logic circuit are placed along a first outer periphery and the intermediate connection wirings are placed to cross in a first direction. The AD converter circuit units are placed along the first direction with two adjacent ones of the AD converter circuit units set as a pair and with the output circuits and the first element circuit parts facing each other for each pair.

Abstract: According to one embodiment, an information processing device includes a buffer and a VSLAM processor. The buffer buffers image data of surroundings of a moving body obtained by an imaging unit of the moving body, and transmits extracted image data extracted based on extracted image determination information from among the buffered image data. The VSLAM processor executes a VSLAM process by using the extracted image data.

Abstract: A map information update method includes: obtaining one or more projection relationships; obtaining, for each projection relationship, reprojection error information; calculating, for each of one or more landmarks, a first sum value based on all items of reprojection error information associated with the landmark; calculating, for each of one or more keyframes, a second sum value based on all items of reprojection error information associated with the keyframe; inferring from the first sum value, for each landmark, a position information update value of an item of position information about the landmark, and updating the item of position information about the landmark using the position information update value; and inferring from the second sum value, for each keyframe, a pose information update value of an item of pose information about the keyframe, and updating the item of pose information about the keyframe using the pose information update value.

Abstract: A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.

Abstract: A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.

Abstract: A monitoring device includes a memory; and a processor configured to execute a process including acquiring image data indicating a change in intensity of incident light from a sensor array, determining a first region to be monitored and a second region not to be monitored in a field of view of the sensor array, and outputting a monitoring result of a moving object based on the image data acquired by the sensor array in the first region.

Abstract: An information processing device includes a memory and a processor configured to obtain first point group information that represents three-dimensional positional information, by using image data captured by a first camera; output second point group information obtained by reducing noise of the first point group information, by using one or more filters; and set filter coefficients of the one or more filters, by using (i) a filter coefficient estimation model trained in advance by using (a) test data for learning that includes image data captured by a second camera and (b) training data based on third point group information that represents three-dimensional positional information obtained by a position sensor, and (ii) observation data that includes the image data captured by the first camera.

Abstract: An image processing device includes an extracting part and a prediction part. The extracting part extracts an unsaturated area, in which pixel values are not saturated, and a saturated area, in which pixel values are saturated, from image data that is captured by an imaging device and that shows an image including a plurality of pixels. The prediction part predicts a pixel value of a pixel of interest in the saturated area based on pixel values of a plurality of border pixels in a border area, the border area being located in the unsaturated area and bordering the saturated area.

Abstract: A sample-and-hold circuit includes a sampling capacitor, a bootstrapped signal sampling switch transistor between an input voltage and a first node of the sampling capacitor, and a common-mode switch transistor connected between a second node of the sampling capacitor and a common-mode voltage. The bootstrapped signal sampling switch transistor is controlled by a gate voltage that is dependent on the input signal voltage so as to provide a substantially signal-independent gate-source voltage to turn on the transistor. The common-mode switch transistor is controlled by a programmable gate voltage such that it becomes possible to trim the series on-resistance of the above-mentioned switch transistors to allow for calibration of a sample-and-hold circuit bandwidth.

Abstract: A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.

Abstract: A memory circuit includes: a plurality of memory parts, each of which includes a plurality of first memory cells and a second memory cell that is accessed when one of the first memory cells is defective; a plurality of first memory control parts, each of which is configured to control access to a corresponding one of the plurality of memory parts based on a first access request addressing the corresponding memory part, during a first mode; and a second memory control part shared by the plurality of memory parts, and configured to control access to the plurality of memory parts based on a second access request during a second mode.

Abstract: A communication method includes: performing carrier sensing at a predetermined time interval; transmitting first data including ID information of a current radio tag to an access point when a signal transmitted by another radio tag to the access point is not detected during the performing of the carrier sensing and the current radio tag is not in a transmission stop state; interpreting a command included in a signal, when the signal is detected during the performing of the carrier sensing and is not a signal transmitted by another radio tag to the access point, the interpreting being performed under an assumption that the signal detected is a signal transmitted from the access point; and changing the radio frequency of a signal to be transmitted by the current radio tag, when the interpreting shows that the signal includes a command instructing changing of a frequency.

Abstract: A semiconductor integrated circuit device includes a ring oscillator having a plurality of stages of delay circuits. In each of the delay circuits, when the signal at the input terminal makes a first transition, the signal at the output terminal transitions in response to the operation of a first transistor that corresponds to a transistor in an SRAM cell. When the signal at the input terminal makes a second transition, the first transistor is electrically isolated from the output terminal, and the signal at the output terminal transitions in response to the operation of a second transistor.

Abstract: In an IO region of a semiconductor integrated circuit device, placed is an IO cell row including a signal IO cell and a power IO cell supplying a first power supply. The power IO cell includes first and second external terminals connected to an external connection pad and an electrostatic discharge (ESD) protection device formed at least in a region between the first and second external terminals. The first external terminal is placed at a position having an overlap in the Y direction with a power supply line for a second power supply.

Abstract: An image processing device is configured to generate a three-dimensional bird's eye view image by projecting captured images acquired from a plurality of imaging devices onto a three-dimensional projection surface, and includes: an acquiring part configured to acquire position information of a first area, on which an object is to be placed, in a three-dimensional space; a conversion part configured to convert the position information of the first area into position information in accordance with the three-dimensional projection surface; and an output part configured to output the three-dimensional bird's eye view image, on which the object is to be placed on a second area in the three-dimensional space, the second area being specified by the converted position information. By this means, when the three-dimensional bird's eye view image is generated from multiple images, it is possible to display the object naturally in the three-dimensional bird's eye view image.