Abstract: An image processing apparatus according to one aspect includes a hardware processor connected to a memory. The hardware processor performs a process including: acquiring a plurality of captured images whose capturing areas overlap with one another; determining whether an object is included in an overlap portion of adjacent ones of the plurality of captured images in a projected image, the projected image being obtained by projecting the plurality of captured images onto a reference projection plane, the reference projection plane being an image projection plane virtually disposed in a virtual space corresponding to a real space; and performing an adjustment process on an overlap area of the reference projection plane, the overlap area including the object on the reference projection plane and corresponding to the overlap portion including the object.

Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.

Abstract: A semiconductor device includes a substrate; first and second fins protruding from the substrate; a first transistor including the first fin; a second transistor above the first transistor; and a first power supply line electrically connected to the first fin through the second fin. The first transistor includes first and second impurity areas in the first fin, and a first gate insulating film on the first fin between the first and second impurity areas. The second transistor includes a first semiconductor area above the first fin, a third impurity area in the first semiconductor area above the first impurity area, a fourth impurity area in the first semiconductor area above the second impurity area, and a second gate insulating film on the first semiconductor area between the third and fourth impurity areas. The first and second transistors have a common gate on the first and second gate insulating films.

Abstract: A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively.

Abstract: An image processing device includes a memory and a processor configured to separate first image data obtained by an image sensor having a Bayer arrangement, into second image data that includes brightness information, and third image data that includes color information and has a lower resolution than the first image data and the second image data, wherein a pixel arrangement of the third image data includes two pixels in each of a horizontal direction and a vertical direction, among which two pixels on one diagonal are of a same type, two pixels on another diagonal are of types different from each other, and the two pixels on said another diagonal are of the types different from the two pixels on the one diagonal.

Abstract: An imaging device includes: an imaging element including a plurality of photoelectric conversion elements arranged in a matrix, and configured to be driven in units of a plurality of lines each including a plurality of photoelectric conversion elements arranged in one direction; a memory; and a processor. The processor is configured to execute detecting an occurrence of a flicker, based on image data generated by the imaging element; and increasing a number of times of exposures in one-frame period of the photoelectric conversion elements included in a line in which the flicker is detected by the detecting, compared with a number of times of exposures in the one-frame period of the photoelectric conversion elements included in a line in which a flicker is not detected.

Abstract: A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.

Abstract: In a wireless reception circuit, an LNA amplifies an input signal, and a mixer mixes the output of the LNA with a local oscillation signal. The output of the mixer is filtered by a first filter circuit, and the signal strength is detected by a first signal strength detection circuit. The output of the mixer is also filtered by a second filter circuit via an attenuator, and the signal strength is detected by a second signal strength detection circuit. The signal strength detected by the first signal strength detection circuit and the signal strength detected by the second signal strength detection circuit are added up to obtain the signal strength of the input signal.

Abstract: A color image inpainting method includes: obtaining a color image of an object to be recognized, the color image including a missing portion where at least part of image information is missing; obtaining an infrared image of the object; identifying the missing portion in the color image; and inpainting the missing portion in the color image identified in the identifying. The inpainting includes inpainting the missing portion by using information which is obtained from the infrared image and corresponds to the missing portion to obtain an inpainted color image of the object.

Abstract: A semiconductor integrated circuit device includes a clock buffer cell that is a standard cell transmitting a clock signal. The clock buffer cell has an input terminal and an output terminal. A first metal interconnect including the output terminal is located in a layer above a second metal interconnect including the input terminal and greater in width than the second metal interconnect.

Abstract: In one aspect, an information processing apparatus includes a first acquisition module, a first extraction module, a first generation module, a second extraction module, a derivation module, and a first output control module. The first acquisition module acquires an input image to output a first image and a second image. The first extraction module extracts first characteristic point information from the first image. The first generation module generates a third image obtained by reducing a data amount of the second image. The second extraction module extracts second characteristic point information from the third image. The derivation module derives a difference between the first characteristic point information and the second characteristic point information. The first output control module outputs the third image corrected in accordance with the difference as an output image.

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

Abstract: The voltage hold circuit is a voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit including: a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every the processing cycle.

Abstract: An information transmission method of a mobile reception terminal that is capable of connecting to a server over a network and capable of receiving a direct wave and a reflected wave of radio waves transmitted by a transmission station that has a fixed position and transmits radio waves of a same modulation scheme continuously or periodically, includes: creating a delay profile of reception of the direct wave and the reflected wave that indicates a time difference between the direct wave and the reflected wave; and transmitting the delay profile to the server over the network.

Abstract: A semiconductor device includes a first wiring; a first circuit region provided with a first power supply wiring and a first ground wiring; a second circuit region provided with a second power supply wiring and a second ground wiring; and a bidirectional diode connected between the first and second ground wirings, and provided with first and second diodes. The first diode includes a first impurity region of a first conductive type, connected to the second ground wiring, and a second impurity region of a second conductive type, connected to the first ground wiring. The second diode includes a third impurity region of the second conductive type connected to the second ground wiring, and a fourth impurity region of the first conductive type connected to the first ground wiring. Any of the first to fourth impurity regions, or any combination of the impurity regions is connected to the first wiring.

Abstract: A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

Abstract: In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.