Abstract: A signal processing method is executed by a signal processing device connected to a radio device that transmits radio waves in given periods and receives reflection waves, to process signals of the reflection waves. The signal processing method includes: obtaining positional information on a moving object at respective times based on the signals of the reflection waves; identifying a coordinate that is a coordinate in an axis in a transmission direction of the radio waves, and satisfies an end condition of a gesture from among the obtained positional information at the respective times; and extracting a group of consecutive coordinates including the identified coordinate as an end point.

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells each connected to a bit line pair; and a write circuit that brings a low potential-side bit line to a negative potential in response to a negative potential boost signal. At the data read operation, a word line is activated after a lapse of a first predetermined time from a transition of an input clock signal, to read the memory value of the memory cell. At the data write operation, the word line is activated after a lapse of a second predetermined time longer than the first predetermined time from a transition of the input clock signal, and the negative potential boost signal is activated after a lapse of a third predetermined time longer than the first predetermined time.

Abstract: A current mirror circuit includes: a plurality of first transistors connected to a first power supply at their sources and to an input terminal at their gates and drains; and a second transistor connected to the first power supply at its source, to the input terminal at its gate, and to an output terminal at its drain. A switch circuit is provided between at least one of the first transistors and the input terminal. The switch circuit includes third and fourth transistors connected in series between the first transistor and the input terminal, an inverter circuit, and a fifth transistor connected between a middle node of the third and fourth transistors and an output terminal of the inverter circuit. A switch control signal is given to the gates of the third to fifth transistors and to the input of the inverter circuit.

Abstract: A common adjustment circuit includes: a first comparator comparing a reference voltage with a voltage between a first transistor and a first resistance and outputting the comparison result; a current mirror circuit including a second transistor allowing an input current to flow through it and a third transistor allowing an output current to flow through it; a replica circuit imitating a differential amplifier; and a second comparator connected to a connection node between the third transistor and a second resistance at one of its inputs and to a replica output node of the replica circuit at the other input, to compare the two inputs and output a bias voltage.

Abstract: A memory circuit includes memory groups each of which includes memory cells, and is configured to execute a write operation or a read operation in response to a request signal; memory group controllers each of which is provided for a corresponding one of the memory groups; and a first memory controller configured to output a request signal received from an outside to an adjacent memory group controller, wherein, in a case where an address signal included in the received request signal indicates the corresponding one of the memory groups, said each of the memory group controllers outputs the request signal to the corresponding one of the memory groups, and in a case where the address signal indicates a memory group other than the corresponding one of the memory groups, outputs the request signal to a memory group controller at a succeeding stage.

Abstract: An output circuit outputs an output signal having an amplitude VCCH responsive to an input signal having an amplitude VCCL. The output circuit includes: first and second p-type transistors connected in series between VCCH and an output terminal; a first n-type transistor grounded at its source and receiving a first signal at its gate; a third p-type transistor connected to VCCH at its source, connected to the gate of the first p-type transistor at its drain, and receiving a second signal at its gate; and a first diode connected between the drains of the first n-type transistor and the third p-type transistor.

Abstract: An image processing apparatus performs a process including acquiring first image data, calculating a white balance value used for an automatic white balance adjustment according to the first image data, performing an automatic white balance adjustment on the first image data according to the white balance value to generate image data after a first correction, calculating a first luminance in the image data after the first correction by adding a color difference component to a luminance, and detecting a first region including a pixel having the first luminance higher than a first threshold value, calculating a correction degree of color information of a pixel included in the first region in the image data after the first correction, according to the first luminance, and correcting the color information of the pixel included in the first region in the image data after the first correction, according to the correction degree.

Abstract: According to one embodiment, an information processing device includes: a first determination module that determines first information concerning deformation of a projection surface on which a peripheral image of a moving body is projected; and a deformation module that deforms the projection surface based on the first information. The first determination module includes an information retaining module that accumulates second information in the past used for determining the first information, and determines the first information based on the second information in the past at an operation start time of the moving body.

Abstract: A loop filter includes: an input terminal and an output terminal mutually connected via a first node; a filter unit; and a low pass filter provided between a second power supply terminal and a third power supply node. One or more of at least one first resistive element and at least one first capacitive element constituting the filter unit are provided between the first node and a first power supply terminal via a switch part, and at least either the resistance value or the capacitance value of the filter unit is variable with on/off of the switch part. The switch part is constituted by transistors, and the backgate of at least one of the transistors is connected to the third power supply node.

Abstract: An AD converter device includes: a plurality of AD converter circuit units which performs analog-to-digital conversion in a time-interleaved manner; and a multiplexer circuit which generates a digital signal from output signals of the AD converter circuit units. The multiplexer circuit includes logic circuits and intermediate connection wirings placed to be distributed in the AD converter circuit units, the logic circuits are connected in a tournament configuration. In each of the AD converter circuit units, an output circuit and a first element circuit part including the logic circuit are placed along a first outer periphery and the intermediate connection wirings are placed to cross in a first direction. The AD converter circuit units are placed along the first direction with two adjacent ones of the AD converter circuit units set as a pair and with the output circuits and the first element circuit parts facing each other for each pair.

Abstract: According to one embodiment, an information processing device includes a buffer and a VSLAM processor. The buffer buffers image data of surroundings of a moving body obtained by an imaging unit of the moving body, and transmits extracted image data extracted based on extracted image determination information from among the buffered image data. The VSLAM processor executes a VSLAM process by using the extracted image data.

Abstract: A map information update method includes: obtaining one or more projection relationships; obtaining, for each projection relationship, reprojection error information; calculating, for each of one or more landmarks, a first sum value based on all items of reprojection error information associated with the landmark; calculating, for each of one or more keyframes, a second sum value based on all items of reprojection error information associated with the keyframe; inferring from the first sum value, for each landmark, a position information update value of an item of position information about the landmark, and updating the item of position information about the landmark using the position information update value; and inferring from the second sum value, for each keyframe, a pose information update value of an item of pose information about the keyframe, and updating the item of pose information about the keyframe using the pose information update value.

Abstract: A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.

Abstract: A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.

Abstract: A monitoring device includes a memory; and a processor configured to execute a process including acquiring image data indicating a change in intensity of incident light from a sensor array, determining a first region to be monitored and a second region not to be monitored in a field of view of the sensor array, and outputting a monitoring result of a moving object based on the image data acquired by the sensor array in the first region.

Abstract: An information processing device includes a memory and a processor configured to obtain first point group information that represents three-dimensional positional information, by using image data captured by a first camera; output second point group information obtained by reducing noise of the first point group information, by using one or more filters; and set filter coefficients of the one or more filters, by using (i) a filter coefficient estimation model trained in advance by using (a) test data for learning that includes image data captured by a second camera and (b) training data based on third point group information that represents three-dimensional positional information obtained by a position sensor, and (ii) observation data that includes the image data captured by the first camera.

Abstract: An image processing device includes an extracting part and a prediction part. The extracting part extracts an unsaturated area, in which pixel values are not saturated, and a saturated area, in which pixel values are saturated, from image data that is captured by an imaging device and that shows an image including a plurality of pixels. The prediction part predicts a pixel value of a pixel of interest in the saturated area based on pixel values of a plurality of border pixels in a border area, the border area being located in the unsaturated area and bordering the saturated area.

Abstract: A sample-and-hold circuit includes a sampling capacitor, a bootstrapped signal sampling switch transistor between an input voltage and a first node of the sampling capacitor, and a common-mode switch transistor connected between a second node of the sampling capacitor and a common-mode voltage. The bootstrapped signal sampling switch transistor is controlled by a gate voltage that is dependent on the input signal voltage so as to provide a substantially signal-independent gate-source voltage to turn on the transistor. The common-mode switch transistor is controlled by a programmable gate voltage such that it becomes possible to trim the series on-resistance of the above-mentioned switch transistors to allow for calibration of a sample-and-hold circuit bandwidth.

Abstract: A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.