Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.

Abstract: A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.

Abstract: A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.

Abstract: A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using serially-connected stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.