Abstract: The present invention relates to a fail-safe control interface including branches for providing signals having a safe state or a non-safe state. Each branch comprises inputs for receiving at least two binary control signals (Si, Si*); a source of a non-safe state (Fe) connectable through a basic chain of elements (14, 15) to an output (Oi) when the control signals realize a predetermined combination; a concurrent checker (17) providing an error detection signal (g1, g2) if the inputs of a pair of its inputs are at predetermined states; and means (14*) for providing a first input of said pair of inputs with a signal corresponding to the state of said output and the second input of said pair of inputs with a signal corresponding to the output of a duplicate chain of the basic chain, this duplicate chain reacting like the basic chain in response to the control signals.

Abstract: A data processing system wherein data are parity encoded for failure checking includes a logic operator generating predetermined signals responsive to input signals via first signal paths including results and carry signals, and a complement generator for generating complements of the predetermined signals responsive to the input signals received through second signal paths which are distinct from the first signal paths. In addition, the data processing system includes a double-rail checker receiving the predetermined signals from the logic operator and the complements from the generating means and for checking the logic operator responsive to the predetermined signals and the compliments and producing an output bit. The data processing system also includes a parity predictor for predicting and generating a parity bit of the results of the logic operator responsive to the output bit of the double-rail checker.