Patents Assigned to Soft Machines, Inc.
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Patent number: 9542187Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch. The method further includes assembling a guest instruction block from the instruction sequence. The guest instruction block is translated to a corresponding native conversion block, wherein an at least one native far branch that corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch. Upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.Type: GrantFiled: January 27, 2012Date of Patent: January 10, 2017Assignee: Soft Machines, Inc.Inventor: Mohammad Abdallah
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Patent number: 9501280Abstract: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.Type: GrantFiled: February 28, 2014Date of Patent: November 22, 2016Assignee: Soft Machines, Inc.Inventor: Mohammad A. Abdallah
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Patent number: 9229873Abstract: Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.Type: GrantFiled: July 30, 2012Date of Patent: January 5, 2016Assignee: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
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Patent number: 9207960Abstract: A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest instruction using a first level conversion table. The method further includes outputting a resulting native instruction when the first level translation proceeds to completion. A second level translation of the guest instruction is performed using a second level conversion table when the first level translation does not proceed to completion, wherein the second level translation further processes the guest instruction based upon a partial translation from the first level conversion table. The resulting native instruction is output when the second level translation proceeds to completion.Type: GrantFiled: January 27, 2012Date of Patent: December 8, 2015Assignee: Soft Machines, Inc.Inventor: Mohammad Abdallah
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Publication number: 20150286576Abstract: Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue cache requests that miss a second cache after missing a first cache. The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache. The apparatus may be further configured to lock the evict way recorded in the additional memory, for example, to prevent reuse of the evict way. The apparatus may be further configured to unlock the evict way responsive to a fill from the second cache to the cache. The additional memory may be a component of a higher level cache.Type: ApplicationFiled: December 16, 2011Publication date: October 8, 2015Applicant: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
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Patent number: 9053292Abstract: A processor has a register file configurable for different execution modes. In one mode the multiple register segments form a single register file where each register segment stores a Multiple Instructions Multiple Data (MIMD) super instruction matrix issuing four simultaneous instruction matrices where each individual instruction within each of the four simultaneous instruction matrices is a scalar or Single Instruction Multiple Data (SIMD). Another execution mode has the multiple register segments forming individual independent register tiles with individual register state to support simultaneous processing of separate threads, where each instruction matrix is associated with a separate thread and a separate register file segment.Type: GrantFiled: November 30, 2012Date of Patent: June 9, 2015Assignee: Soft Machines, Inc.Inventor: Mohammad A. Abdallah
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Publication number: 20150067230Abstract: Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Paul Chan
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Publication number: 20150052401Abstract: Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: Soft Machines, Inc.Inventors: Karthikeyan AVUDAIYAPPAN, Brian MCGEE
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Publication number: 20150052303Abstract: A method for acquiring cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method, a store queue is accessed for one or more portions of a cache line associated with a load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Paul G. Chan
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Publication number: 20150052304Abstract: Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding the read transaction with the phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to the read transaction. The phantom read transaction identifier acts as a pointer to a real read transaction identifier.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: Soft Machines, Inc.Inventor: Karthikeyan Avudaiyappan
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Publication number: 20150046683Abstract: A method for executing instructions using register templates to track interdependencies among blocks of instructions. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; and using a register template to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions.Type: ApplicationFiled: March 14, 2014Publication date: February 12, 2015Applicant: Soft Machines, Inc.Inventor: Mohammad A. Abdallah
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Publication number: 20150046686Abstract: A method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templates.Type: ApplicationFiled: March 14, 2014Publication date: February 12, 2015Applicant: Soft Machines, Inc.Inventor: Mohammad A. Abdallah
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Patent number: 8930674Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.Type: GrantFiled: March 7, 2012Date of Patent: January 6, 2015Assignee: Soft Machines, Inc.Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
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Publication number: 20140373022Abstract: A method for performing instruction scheduling in an out-of-order microprocessor pipeline is disclosed. The method comprises selecting a first set of instructions to dispatch from a scheduler to an execution module, wherein the execution module comprises two types of execution units. The first type of execution unit executes both a first and a second type of instruction and the second type of execution unit executes only the second type. Next, the method comprises selecting a second set of instructions to dispatch, which is a subset of the first set and comprises only instructions of the second type. Next, the method comprises determining a third set of instructions, which comprises instructions not selected as part of the second set. Finally, the method comprises dispatching the second set for execution using the second type of execution unit and dispatching the third set for execution using the first type of execution unit.Type: ApplicationFiled: December 16, 2013Publication date: December 18, 2014Applicant: Soft Machines, Inc.Inventor: Nelson N. CHAN
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Publication number: 20140324937Abstract: A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.Type: ApplicationFiled: March 14, 2014Publication date: October 30, 2014Applicant: Soft Machines, Inc.Inventor: Mohammad Abdallah
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Publication number: 20140317351Abstract: A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.Type: ApplicationFiled: February 18, 2014Publication date: October 23, 2014Applicant: Soft Machines, Inc.Inventors: Ravishankar RAO, Nishit SHAH
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Publication number: 20140317387Abstract: A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and performing a dual dispatch of the two half blocks for execution on an execution unit.Type: ApplicationFiled: March 14, 2014Publication date: October 23, 2014Applicant: Soft Machines, Inc.Inventor: Mohammad ABDALLAH
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Publication number: 20140304492Abstract: A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ) is disclosed. The method comprises initiating a computation of a virtual address corresponding to the load instruction in a first clock cycle. It also comprises transmitting early calculated lower address bits of the virtual address to a load store queue (LSQ) in the same cycle as the initiating. Finally, it comprises performing a partial match in the LSQ responsive to and using the lower address bits to find a prior aliasing store, wherein the prior aliasing store stores to a same address as the load instruction.Type: ApplicationFiled: May 19, 2014Publication date: October 9, 2014Applicant: Soft Machines, Inc.Inventors: Mohammad A. ABDALLAH, Ravishankar RAO
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Publication number: 20140281409Abstract: A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: Soft Machines, Inc.Inventors: Mohammad A. ABDALLAH, Mandeep SINGH
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Publication number: 20140281416Abstract: A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of multiplexers to access ports of a scheduling array to store the instruction blocks as a series of chunks.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Soft Machines, Inc.Inventor: Mohammad A. Abdallah