Abstract: In a method of testing a semiconductor wafer or sample having a dielectric layer overlaying a substrate of semiconducting material, a contact is caused to touch a top surface of the dielectric layer. At least a portion of the contact touching the dielectric layer is formed of iridium. A controlled electrical stimulus that causes the dielectric layer to breakdown and an electrically conductive path to form through the dielectric layer is applied to the contact touching the top surface of the dielectric layer. Either a value of the controlled electrical stimulus where breakdown of the dielectric layer occurs or a time for the breakdown of the dielectric layer to occur in response to the application of the controlled electrical stimulus is determined. From the thus determined value or time, a determination can be made whether the dielectric layer is within acceptable tolerance.

Abstract: By using techniques for near field probes to measure dielectric values of blanket films, the measure of the sidewall damage of the patterned structure is calculated. The interaction between the near field probe and the etched structure is modeled to obtain the model total capacitance. The near field microwave probe is calibrated on a set of blanket films with different thicknesses, and the dielectric constant of the etched trench structure is calculated using the measured frequency shift and calibration parameters. The measured capacitance is further calculated for the etched trench structure using the dielectric constant and the total thickness of the etched trench structure. The effective dielectric constant of the structure under study is extracted where the model capacitance is equal to the measured capacitance. The measure of the sidewall damage is further calculated using the effective dielectric constant.

Abstract: A semiconductor wafer or sample having a substrate of semiconducting material is tested by compressing a dielectric between three electrically conductive contacts and a top surface of the semiconductor wafer or sample substrate. The dielectric has a thickness that permits tunneling current to flow therethrough without damaging the dielectric. A first electrical bias is applied to a pair of adjacent contacts and a second electrical bias, such as ground reference, is applied to the other contact whereupon an inversion layer forms in the semiconductor wafer or sample. A value of a current that flows in the semiconductor wafer or sample substrate and across the dielectric, in the form of a tunneling current, is measured in response to the applied electrical biases. A surface mobility of minority carriers in the semiconductor wafer or sample is determined as a function of the applied electrical biases and the value of the measured current.

Abstract: A semiconductor wafer is tested by heating an electrical contact to a temperature sufficient to desorb water vapor and/or organic material from a surface thereof. The semiconductor wafer is also heated to a temperature sufficient to desorb water vapor and/or organic material from a top surface thereof. The heated surface of the contact is caused to touch the heated top surface of the semiconductor wafer. An electrical stimulus is applied between the heated surface of the contact and the heated top surface of the semiconductor wafer when the surface of the contact is touching the top surface of the semiconductor wafer. A response of the semiconductor wafer to the applied electrical stimulus is measured and at least one electrical property of the semiconductor wafer is determined from the measured response.

Abstract: In a method and apparatus for determining one or more electrical properties of a semiconductor wafer or sample, the response of a semiconductor wafer or sample to an applied CV-type electrical stimulus is measured. Utilizing a recursive technique, progressively more accurate values of equivalent oxide thickness CET, maximum capacitance Cox, flatband voltage Vfb and other properties of the semiconductor wafer or sample are determined from the measured response. An equivalent oxide thickness EOT of the semiconductor wafer or sample can be determined as a function of the most accurate value of CET determined based upon convergence of at least one of (1) the last two values of Cox or (2) the last two values of Vfb within a predetermined convergence criteria. One or more of the EOT value and/or values of one or more of CET, Cox or Vfb can then be output in a human detectable form.

Abstract: In a method of determining that a semiconductor wafer or sample has a desirable density of electrically active dopant, minimum and maximum capacitances associated with the semiconducting material forming the wafer or sample at a first point adjacent a topside thereof are determined and minimum and maximum capacitances associated with the semiconducting material forming the wafer or sample at a second point adjacent a beveled surface thereof that is defined by the removal of a portion of the topside thereabove are determined. As a function of the minimum and maximum capacitances determined at each point and the depth on or from the topside surface where each point resides, the electrically active dopant density of the semiconductor wafer or sample can be determined.

Abstract: A measurement technique based on a microwave near-field scanning probe is developed for non-contact measurement of dielectric constant of low-k films. The technique is non-destructive, non-invasive and can be used on both porous and non-porous dielectrics. The technique is based on measurement of resonant frequency shift of the near-field microwave resonator for a plurality of calibration samples vs. distance between the probe tip and the sample to construct a calibration curve. Probe resonance frequency shift measured for the sample under study vs. tip-sample separation is fitted into the calibration curve to extract the dielectric constant of the sample under study. The calibration permits obtaining a linear calibration curve in order to simplify the extraction of the dielectric constant of the sample under study.

Abstract: A method of measuring at least one electrical property of a semiconductor wafer includes providing an elastically deformable and electrically conductive contact having an insulative oxide layer formed on an exterior surface thereof by a controlled oxidation process, such as, without limitation, thermal oxidation, anodic oxidation or deposition oxidation. A first electrical contact is formed between the oxide layer on the surface of the contact and a dielectric layer overlaying a top surface of the semiconductor wafer and a second electrical contact is formed with the semiconductor wafer. A CV type stimulus is applied between the first electrical contact and the second electrical contact. A response of the semiconductor wafer to the CV type stimulus is measured and at least one electrical property of the dielectric layer, the semiconductor wafer or both is determined from the response.

Abstract: A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is made whether the ion implantation is within acceptable tolerance(s).

Abstract: A semiconductor wafer or sample having a substrate of semiconducting material is tested by compressing a dielectric between three electrically conductive contacts and a top surface of the semiconductor wafer or sample substrate. The dielectric has a thickness that permits tunneling current to flow therethrough without damaging the dielectric. A first electrical bias is applied to a pair of adjacent contacts and a second electrical bias, such as ground reference, is applied to the other contact whereupon an inversion layer forms in the semiconductor wafer or sample. A value of a current that flows in the semiconductor wafer or sample substrate and across the dielectric, in the form of a tunneling current, is measured in response to the applied electrical biases. A surface mobility of minority carriers in the semiconductor wafer or sample is determined as a function of the applied electrical biases and the value of the measured current.

Abstract: To determine a concentration of defects and/or impurities in a semiconductor wafer, a first value of current is caused to flow in the semiconductor wafer having a substrate of semiconducting material. The semiconductor wafer is exposed to a pulse of light whereupon electron-hole pairs generated in the semiconductor wafer in response to the light pulse cause the current to increase to a second value. After termination of the light pulse, the rate of change of the current from the second value toward the first value is determined. A concentration of defects and/or impurities in the semiconductor wafer is determined as a function of the rate of change.

Abstract: In a method and apparatus for determining one or more electrical properties of a semiconductor wafer or sample, the response of a semiconductor wafer or sample to an applied CV-type electrical stimulus is measured. Utilizing a recursive technique, progressively more accurate values of equivalent oxide thickness CET, maximum capacitance Cox, flatband voltage Vfb and other properties of the semiconductor wafer or sample are determined from the measured response. An equivalent oxide thickness EOT of the semiconductor wafer or sample can be determined as a function of the most accurate value of CET determined based upon convergence of at least one of (1) the last two values of Cox or (2) the last two values of Vfb within a predetermined convergence criteria. One or more of the EOT value and/or values of one or more of CET, Cox or Vfb can then be output in a human detectable form.

Abstract: A method of measuring at least one electrical property of a semiconductor wafer includes providing an elastically deformable and electrically conductive contact having an insulative oxide layer formed on an exterior surface thereof by a controlled oxidation process, such as, without limitation, thermal oxidation, anodic oxidation or deposition oxidation. A first electrical contact is formed between the oxide layer on the surface of the contact and a dielectric layer overlaying a top surface of the semiconductor wafer and a second electrical contact is formed with the semiconductor wafer. A CV type stimulus is applied between the first electrical contact and the second electrical contact. A response of the semiconductor wafer to the CV type stimulus is measured and at least one electrical property of the dielectric layer, the semiconductor wafer or both is determined from the response.

Abstract: A method of processing a semiconductor wafer includes utilizing a heated gas to heat at least one part of a semiconductor wafer by convection whereupon at least one contaminant is desorbed therefrom. A stream of cooling gas is caused to pass over the one part of the semiconductor wafer in the absence of heated gas to cool the one part of the semiconductor wafer. A metrology tool is then caused to measure at least one part of the semiconductor wafer to determine at least one characteristic thereof.

Abstract: A semiconductor wafer is tested by heating an electrical contact to a temperature sufficient to desorb water vapor and/or organic material from a surface thereof. The semiconductor wafer is also heated to a temperature sufficient to desorb water vapor and/or organic material from a top surface thereof. The heated surface of the contact is caused to touch the heated top surface of the semiconductor wafer. An electrical stimulus is applied between the heated surface of the contact and the heated top surface of the semiconductor wafer when the surface of the contact is touching the top surface of the semiconductor wafer. A response of the semiconductor wafer to the applied electrical stimulus is measured and at least one electrical property of the semiconductor wafer is determined from the measured response.

Abstract: To determine the generation lifetime of a pn junction of a semiconductor wafer, an elastically deformable, electrically conductive contact is caused to touch a surface of the semiconductor wafer over the pn junction. At least one reverse bias voltage is applied to the pn junction via the contact and a value of current flowing in the contact in response to the application of each reverse bias voltage is measured. The generation lifetime of the pn junction is then determined from a subset of the values of the reverse bias voltage and the corresponding values of measured current.

Abstract: In an apparatus and method for determining a permittivity of a dielectric layer on a semiconductor wafer, a thickness of the dielectric layer is determined and a topside of the wafer is moved into contact with a spherical portion of an at least partially spherical and electrically conductive surface. An electrical stimulus is applied between the electrically conductive surface and the semiconducting material. A capacitance of a capacitor comprised of the electrically conductive surface, the semiconductor material and the dielectric layer is determined from the applied stimulus. A permittivity of the dielectric layer is then determined as a function of the capacitance and the thickness of the dielectric layer.

Abstract: In a method of measuring at least one electrical property of a semiconductor wafer, an elastically deformable conductive contact formed from an electrically conductive coating overlaying an electrically conductive base material is provided. The base material has a first work function and the coating has a second work function. A first electrical contact is formed between the conductive contact and a top surface of a semiconductor wafer. A second electrical contact is formed with the semiconductor wafer. An electrical stimulus is applied between the first and second electrical contacts and a response of the semiconductor wafer to the electrical stimulus is measured. At least one electrical property of the semiconductor wafer is determined from the response.

Abstract: To determine a concentration of defects and/or impurities in a semiconductor wafer, a first value of current is caused to flow in the semiconductor wafer having a substrate of semiconducting material. The semiconductor wafer is exposed to a pulse of light whereupon electron-hole pairs generated in the semiconductor wafer in response to the light pulse cause the current to increase to a second value. After termination of the light pulse, the rate of change of the current from the second value toward the first value is determined. A concentration of defects and/or impurities in the semiconductor wafer is determined as a function of the rate of change.

Abstract: A current-voltage response of at least one site of a semiconductor wafer where ions have been implanted in the semiconducting material of the semiconductor wafer is measured prior to annealing the semiconductor wafer. From the measured response, a determination is made whether the ion implantation is within acceptable tolerance(s).