Patents Assigned to Solid-State Research, Inc.
  • Patent number: 7749789
    Abstract: A process producing a single-crystalline device fabricated on a single-sided polished wafer employing processing from only the front-side and having a significant separation between the device and substrate is provided. In one embodiment, a method comprises an upper layer and a lower substrate. A device is formed in the upper layer, defined by gaps. The gaps are filled with at least one material that has etch characteristics different from those of the device and the substrate. At least a top portion of the gap material is removed from the upper layer. The gap material is etched so that a portion of the gap-material remains on the sidewalls of the surrounding upper layer. The material beneath the device is then etched, excluding an insulating layer beneath the device, releasing the device from the substrate. The insulating material beneath the device is then etched, the etch being selective to the insulating material and the gap material.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: July 6, 2010
    Assignee: Solid-State Research, Inc.
    Inventor: Demetrios P Papageorgiou