Abstract: A CMOS EPROM is made wherein the typical EPROM device is an N-channel IGFET having a control gate self-aligned with an underlying floating gate. In this process the EPROM floating gate and the gates of both the P-channel and N-channel peripheral circuit transistors are formed from a first deposited polysilicon layer. The EPROM control gate is formed from a second deposited polysilicon layer. This CMOS EPROM process employs a surprisingly few photoresist steps and is compatible with a high temperature oxidation step for making a very high quality intergate polysilicon oxide in the EPROM devices.

Abstract: A process for making an integrated cirucit EPROM having an array of EPROM devices and CMOS peripheral circuits, including blanket depositions of a first and a second polysilicon layers on a silicon substrate and removing portions of those polysilicon layers. The EPROM floating gate is made from the first polysilicon layer, and the EPROM control gate as well as the P-channel and N-channel gates of the peripheral transistors are all made from the second polysilicon layer. Independently adjustable thresholds for each of the three device types are made possible by forming an N-well at the substrate region at which the P-channel device is to be built, blanket implanting all three channels prior to selectively forming the first polysilicon layer over the EPROM region, and then selectively doping the channels of the N- and P-channel devices only.

Abstract: A CMOS EPROM or the like is made wherein the basic memory device or EPROM device is an N-channel IGFET (insulated gate field effect transistor) having a control gate self-aligned with an underlying floating gate. The sources and drains of the EPROM devices as well as the sources and drains of peripheral N-channel transistors, are made by implanting with arsenic and with phosphorous. When heated, the faster diffusing phosphorous outruns, and extends from the bulk of, the arsenic so that these sources and drains extend slightly under the adjacent gate. This extension of the drain in the memory device enables a faster programming capability. A similar but oppositely directed lateral extension of all these sources and drains reduces the leakage to the substrate and reduces the chances of shorts to the substrate due to slightly misaligned metal to source and drain contacts.

Abstract: CMOS transistors are fabricated in a P substrate using N- well regions. These wells are positioned to prevent aluminum spiking in the N channel devices. After P guard rings are formed for both P and N channel devices, additional masking and implantation are performed to produce N guard rings in the P channel devices. Before the transistors are formed, an implantation of P type impurities is performed causing the P channel devices, when they are formed, to have a PMOS buried channel.

Abstract: A stable sense rail amplifier for CMOS memories is provided allowing very small voltage swings at or very close to the power supply rail to be transformed into substantially rail-to-rail swings. The input of the amplifier is coupled to the output of memory cells which may be designed to have output swings of 200 millivolts or less. These output swings are shifted to approximately the center of the range between the supply voltage and ground. While the level shifting is performed a small amount of linear gain is added. Subsequently the shifted signal is applied to a linear high gain amplifier stage. The high gain amplifier has as its output a substantially rail-to-rail signal. The total delay from the input rail of the amplifier to the high gain inverting amplifier stage is limited to the transfer time of a single CMOS FET. The amplifier is self-biasing and self-referencing.

Abstract: A seal for a semiconductor device in which the semiconductor has a major surface with a metal layer overlying the major surface. An insulating layer of glass is formed on the metal layer and a passive sealing silicon layer is formed on the glass layer for protecting the device from contamination.

Abstract: A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.

Abstract: A semiconductor device which provides in an input circuit a substantially low reactance and a relatively high resistance within a range of operating frequencies to improve the impedance match between the device and an energy source. The device has a semiconductor die with at least a first and a second bonding terminal having capacitance and resistance between the bonding terminals. At least a first bond lead electrically connects the first bonding terminal to a first metallic contact area. Means connects at least a second bond lead between the second bonding terminal and a second metallic contact area. At least a third bond lead electrically connects the first bonding terminal to the second metallic contact area to form an inductance to interact with the capacitance of the semiconductor die within the operating range of frequencies thereby to increase the input impedance.

Abstract: A crystal controlled oscillator has a substantially stable frequency in an environment of wide power supply potential changes. A first CMOS device of a pair is coupled to a crystal network and operates as a substantially small signal linear amplifier. A second CMOS device of the pair forms a constant current source for the first device by means of a plurality of diodes coupled in series circuit between two terminals of the second device to produce a substantially constant biasing potential for the second device only when the potential of the power supply exceeds the value of the diode drop potentials. In this manner, the voltage across the oscillator is relatively independent of power supply voltage changes to provide frequency stability over those changes.

Abstract: A CMOS bistable semiconductor flip-flop circuit having a storage element formed by a first and a second inverter. The output of the second inverter is directly connected to the input of the first inverter. The first inverter output is coupled to the second inverter input through a high resistance feedback of resistance value which is substantially high with respect to the low output impedance of the first inverter. A charge storage device and gates alternately store the state of the storage element and thereafter provide the stored signal to the second inverter input. Additionally, a device is connected to the input of the second inverter to provide a reset or set function.

Abstract: A high speed dynamic CMOS flip-flop system having a master and a slave section each of which have a different total propagation delay. Asymmetrical clock signals are applied to the master and slave sections with one cycle portion of each clock signal turning on the master section and the other cycle turning on the slave section. Each cycle portion has a time duration substantially equal to the total propagation delay of its respective master and slave section. In this manner, the duty cycle of the clock signal cycle is matched to the ratio of the propagation delays of the master and slave sections.

Abstract: A voltage controlled oscillator whose frequency is a function of an input voltage having a first and a second pair of switching devices coupled respectively to first and second terminals of a capacitor. The oscillator has a first leg coupled from the first capacitor terminal through first inverter means, a first NOR device and third inverter means back to the first pair of switching devices and the first capacitor terminal. The second leg is coupled from the second capacitor terminal through second inverter means, a second NOR device, fourth inverter means back to the second pair of switching devices and the second capacitor terminal. The first and second NOR devices are directly cross-connected. The first and second legs each have the same number of propagation delays and during state transition, both terminals of the capacitor are coupled to the reference potential for a brief instant of time.

Abstract: A first subset of semiconductor devices has an associated first additional device and a first gate output. A second subset of semiconductor devices has an associated second additional device and a second gate output. The first and second subsets are of one conductivity type while the first and second additional devices are of another conductivity type. First logic signals are applied to the first subset for turning on the first subset and the first additional device for producing at the first gate output a first function of the first logic signals. Second logic signals are applied to the second subset for turning on the second subset and the second additional device for producing at the second gate output a second function of the second logic signals.

Abstract: A solid state timepiece having a chain of series connected counters with clock pulses being applied to the first counter in the chain. A reset system is responsive to reset signals and is coupled to the counters for selective resetting of the counters upon application of predetermined reset signals. A decoder system independent of the resetting of the counters detects the state of the reset signals during a predetermined time duration and produces a control signal upon application of selected reset signal states. A control system provides internal control of the timepiece only upon application of the control signal.