Abstract: An improved multi-bit memory cell includes a storage capacitor and a switching element coupled to one of the terminals of the capacitor. The switching element includes a first switching component having a positive threshold, and a complementary switching component having a negative threshold. Because the switching element is constructed in this manner, noise generation caused by activation of the switching components is significantly reduced, and cut-off effects are eliminated. Both of these factors contribute to the memory cell's ability to store more bits of information than prior art memory cells.

Abstract: A random access memory, having multi-bit memory cells, includes a successive approximation analog-to-digital (SAAD) converter and a comparator for reading data from the memory cells. In reading data from a cell, the SAAD generates a first reference voltage. This first reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a first comparison result. Based on this first comparison result, a first bit of data is determined. Thereafter, the SAAD generates a second reference voltage based on the first reference voltage and the first comparison result. This second reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a second comparison result. Based on this second comparison result, a second bit of data is determined.

Abstract: A semiconductor memory device according to the present invention comprises a number of memory cells that store multiple voltage levels. Each voltage level is uniquely assigned to a different logic level. Multiple binary codes are converted to various analog voltage levels by a digital to analog converter. The memory cell of the invention comprises a storage capacitor and transfer gates, each terminal of which is connected to a bit line through the transfer gate for isolating the storage capacitor from the interference of other circuits while it is not accessed. In the writing cycle, analog voltage can be stored in the storage capacitor of each cell by applying the assigned analog voltage generated by the digital to analog converter through, bit lines and the transfer gates that control the conductivity between the bit lines and storage capacitor.