Abstract: A method and system to estimate failure rates in designs. N Monte Carlo samples are drawn from the random distribution that describes process variation in the design. A subset of these samples is selected, and that subset of Ninit samples are simulated (with a circuit simulator) to measure a performance value for each sample. A model is constructed, using the values of the Ninit process points as training inputs, and the corresponding Ninit performance values as training outputs. The candidate Monte Carlo samples are from the N Monte Carlo samples that have not yet been simulated. Each candidate is simulated on the model to get predicted performance values, and the samples are ordered in ascending (or descending) order of the predicted performance values. Simulation of candidates samples is then begun, in that order. The sampling and simulation will stops once there is sufficient confidence that all failures are found.

Abstract: A method for finding the process, voltage, temperature, parasitics, and power settings (PVTPP) corner at which an electrical circuit design has the worst-case optimum simulated output performance. The method uses a global optimization process in a series of iterations that aim to uncover the PVTPP corner at which the ECD has the worst-case output value. By using the present method, a designer does not have to simulate the ECD at each and every PVTPP corner, which can same considerable time or compute effort. Examples using Model-Building Optimization are provided.

Abstract: A system and method to analyze analog, mixed-signal, and custom digital circuits. The system and method displays to a user characteristic values of a circuit and statistical uncertainty values of the characteristic values early in a sampling or characterization run of the circuit. The characteristic values and their statistical uncertainties are updated as the sampling or characterization run progresses. The user can halt the sampling or characterization run once a desired level of uncertainty is attained. The system can automatically halt the sampling or characterization run, once the statistical uncertainty lie within a pre-determined range.

Abstract: A method and system to estimate failure rates in designs. N Monte Carlo samples are drawn from the random distribution that describes process variation in the design. A subset of these samples is selected, and that subset of Ninit samples are simulated (with a circuit simulator) to measure a performance value for each sample. A model is constructed, using the values of the Ninit process points as training inputs, and the corresponding Ninit performance values as training outputs. The candidate Monte Carlo samples are from the N Monte Carlo samples that have not yet been simulated. Each candidate is simulated on the model to get predicted performance values, and the samples are ordered in ascending (or descending) order of the predicted performance values. Simulation of candidates samples is then begun, in that order. The sampling and simulation will stops once there is sufficient confidence that all failures are found.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to extract circuit-specific process/environmental corners that is yield-aware and/or specification-aware. Simulation data from previous Monte Carlo-based verification actions can be re-used.

Abstract: A system and method that does trustworthy multi-objective structural synthesis of analog circuits, and extracts expert analog circuit knowledge from the resulting tradeoffs. The system defines a space of thousands of possible topologies via a hierarchically organized combination of designer-trusted analog building blocks, the resulting topologies are guaranteed trustworthy. The system can perform a search based on a multi-objective evolutionary algorithm that uses an age-layered population structure to balance exploration vs. exploitation, with operators that make the search space a hybrid between vector-based and tree-based representations. A scheme employing average ranking on Pareto fronts is used to handle a high number of objectives. Good initial topology sizings are quickly generated via multi-gate constraint satisfaction.

Abstract: A method for finding the process, voltage, temperature, parasitics, and power settings (PVTPP) corner at which an electrical circuit design has the worst-case optimum simulated output performance. The method uses a global optimization process in a series of iterations that aim to uncover the PVTPP corner at which the ECD has the worst-case output value. By using the present method, a designer does not have to simulate the ECD at each and every PVTPP corner, which can same considerable time or compute effort. Examples using Model-Building Optimization are provided.

Abstract: An apparatus and method to generate and evolve canonical form expressions representing a characteristic of a given system. Static and dynamic behavior of non-linear electrical circuits can be modeled. Searching of canonical form expressions can use evolutionary algorithms, simulated annealing and Tabu searching.

Abstract: For application to analog, mixed-signal, and custom digital circuits, as well as other fields have use for high-dimensional regression, or symbolic modeling, a system and method to extract functions, where each function relates a set of input variables to an output variable (performance metric). The technique enumerates a large set of candidate basis functions, performs pathwise regularized learning on those basis functions to generate a set of candidate models, and finally performs nondominated filtering to identify models that trade off complexity versus error.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to extract circuit-specific process/environmental corners that is yield-aware and/or specification-aware. Simulation data from previous Monte Carlo-based verification actions can be re-used.

Abstract: A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to begin with a complex problem description that encompasses many variables from statistical manufacturing, the circuit's environment, and the circuit's design parameters, but then apply techniques to prune the scope of the problem to make it manageable for manual design and more efficient automated design, and finally use that pruned problem for more efficient and effective design.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO can perform global yield optimization on hundreds of variables, with no simplifying assumptions. GSC can capture and display mappings from design variables to performance, across the whole design space. GSC can handle hundreds of design variables in a reasonable time frame, e.g., in less than a day, for a reasonable number of simulations, e.g., less than 100,000. GSC can capture design variable interactions and other possible nonlinearities, explicitly capture uncertainties, and intuitively display them. GSD can support the user's exploration of design-to-performance mappings with fast feedback, thoroughly capturing design variable interactions in the whole space, and allow for more efficiently created, more optimal designs.

Abstract: A method and system for performing multi-objective optimization of a multi-parameter design having several variables and performance metrics. The optimization objectives include the performance values of surrogate models of the performance metrics and the uncertainty in the surrogate models. The uncertainty is always maximized while the performance metrics can be maximized or minimized in accordance with the definitions of the respective performance metrics. Alternatively, one of the optimization objectives can be the value of a user-defined cost function of the multi-parameter design, the cost function depending from the performance metrics and/or the variables. In this case, the other objective is the uncertainty of the cost function, which is maximized. The multi-parameter designs include electrical circuit designs such as analog, mixed-signal, and custom digital circuits.

Abstract: A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to improve the flow of setting up a set of simulations, a characterization, or optimization problem via an interactive circuit schematic. A system and method to visualize circuit simulation data in which at least one of the views is an enhanced, interactive schematic view.

Abstract: A system and method of generating a set of circuit simulation data, applying data mining to for knowledge extraction from the data, and graphically presenting the extracted knowledge in a format that is easy to digest to a designer.

Abstract: A system that includes a candidate generator that generates candidate vectors having as components performance specifications of an electrical circuit design. The system also includes a performance estimator that generates performance vectors of the electrical circuit design, the performance vectors having as components performance values of the electrical circuit design. The candidate vectors and the performance vectors are input into a statistical estimator that calculates a statistical parameter, for example, yield, for each candidate vector in accordance with the performance vectors. The system further includes a filter that receives the candidate vectors and their respective statistical parameters, and outputs a filtered candidate vector with its corresponding filtered statistical parameter. A display system visually represents the filtered candidate vector and its corresponding filtered statistical parameter.

Abstract: A system and method that does trustworthy multi-objective structural synthesis of analog circuits, and extracts expert analog circuit knowledge from the resulting tradeoffs. The system defines a space of thousands of possible topologies via a hierarchically organized combination of designer-trusted analog building blocks, the resulting topologies are guaranteed trustworthy. The system can perform a search based on a multi-objective evolutionary algorithm that uses an age-layered population structure to balance exploration vs. exploitation, with operators that make the search space a hybrid between vector-based and tree-based representations. A scheme employing average ranking on Pareto fronts is used to handle a high number of objectives. Good initial topology sizings are quickly generated via multi-gate constraint satisfaction.

Abstract: For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO can perform global yield optimization on hundreds of variables, with no simplifying assumptions. GSC can capture and display mappings from design variables to performance, across the whole design space. GSC can handle hundreds of design variables in a reasonable time frame, e.g., in less than a day, for a reasonable number of simulations, e.g., less than 100,000. GSC can capture design variable interactions and other possible nonlinearities, explicitly capture uncertainties, and intuitively display them. GSD can support the user's exploration of design-to-performance mappings with fast feedback, thoroughly capturing design variable interactions in the whole space, and allow for more efficiently created, more optimal designs.