Abstract: A semiconductor circuit capable of keeping the leakage current to a minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to a maximum, wherein delay paths to which low threshold voltage gate elements are applied are restricted to delay paths in a range from a maximum delay value before a lowering of a threshold voltage (at a higher speed than this) to a new maximum delay value in a case where low threshold voltage gate elements are applied to this (at a lower speed than this), whereby a leakage current due to low threshold voltage transistors can be kept to the minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to the maximum, thereby solving the problem of an unrequired leakage current applied to a chip over a wide range.