Patents Assigned to Sony Corporaiton
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Patent number: 10621994Abstract: The present technology relates to an audio signal processing device and method, an encoding device and method, and a program, which are capable of obtaining a higher quality sound. A selection unit selects, from supplied multichannel audio signals, audio signals of a channel of a dialogue sound and audio signals of a channel to be downmixed. A downmixing unit downmixes the audio signals of the channel to be downmixed. An addition unit adds the audio signals of the channel of a dialogue sound to audio signals of a predetermined channel among audio signals of one or more channels obtained in the downmixing. The present technology can be applied to a decoder.Type: GrantFiled: May 22, 2015Date of Patent: April 14, 2020Assignee: Sony CorporaitonInventors: Mitsuyuki Hatanaka, Toru Chinen, Minoru Tsuji, Hiroyuki Honma
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Publication number: 20130215222Abstract: [Object] To easily realize maintaining of consistency in perspective with each object in an image, when displaying superimposing information at the time of stereoscopic image display, such as graphics information like OSD for example. [Solution] A depth information output unit outputs depth information corresponding to a stereoscopic image. The depth information includes division information of an image display plane and depth information of the division regions. The depth information is, for example, image plane information indicating whether or not a stereoscopic image plane is on the near side from a monitor position, and further, this image plan information and disparity information. Flag information indicating the existence of the disparity information is inserted into the depth information. The depth information is included in a descriptor inserted underneath PMT or EIT or the like of a multiplexed data stream, and transmitted.Type: ApplicationFiled: November 1, 2011Publication date: August 22, 2013Applicant: SONY CORPORAITONInventor: Ikuo Tsukagoshi
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Patent number: 8487273Abstract: A microchip includes a sample liquid feed channel permitting a sample liquid containing particulates to flow through, at least one pair of sheath liquid feed channels configured to merge to the sample liquid feed channel from both sides thereof for permitting a sheath liquid to flow through surrounding the sample liquid, a merging channel connected to the sample liquid feed channel and the one pair of the sheath liquid feed channels for permitting the sample liquid and the sheath liquid to merge and flow through the merging channel, a vacuum suction unit for drawing into the particulate subject to collection, connected to the merging channel, and at least one pair of discharge channels formed on both sides of the vacuum suction unit for permitting to flow through from the merging channel.Type: GrantFiled: December 8, 2011Date of Patent: July 16, 2013Assignee: Sony CorporaitonInventors: Tatsumi Ito, Masaya Kakuta, Shingo Imanishi, Nao Nitta, Koji Futamura, Toru Takashimizu, Koji Ashizaki, Motohiro Furuki
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Patent number: 7561576Abstract: In order to predictively time stamp isochronous data packets transmitted over an IEEE 1394-1995 serial bus network, an application, which is to send a stream of isochronous data packets to a receiving node, first transmits a number of dummy frames each consisting of a number of packets. Preferably, these isochronous data packets make up frames of video data. From these dummy packets, the application obtains the time stamp values within the common isochronous packet (CIP) header of each packet. Using these obtained time stamp values, the application calculates a presentation time value for each data frame to be transmitted. The obtained time stamp value from a transmitted video frame is used to calculate the presentation time for a video frame which is a number of frames ahead within the transmit queue.Type: GrantFiled: September 19, 2005Date of Patent: July 14, 2009Assignees: Sony Corporaiton, Sony Electronics Inc.Inventors: Kevin K. Lym, Hisato Shima, Quan Vu
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Publication number: 20060114134Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.Type: ApplicationFiled: January 10, 2006Publication date: June 1, 2006Applicant: Sony CorporaitonInventors: Makoto Noda, Hiroyuki Yamagishi
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Patent number: 5812735Abstract: Error start codes are inserted, by means of error start code inserting section (12), between transfer units of intra-frame coded data starting from a start code reproduced by reproducing section (11) from picture recording medium (10) to decode intra-frame coded data on the basis of the error start code and the start code at decoder (14).Type: GrantFiled: April 7, 1997Date of Patent: September 22, 1998Assignee: Sony CorporaitonInventor: Tohru Wada
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Patent number: 5029190Abstract: An output circuit for CCD imager devices or CCD delay devices is disclosed in which a depletion type second MIS transistor is connected to the drain side of a first MIS transistor constituting a source follower adapted for converting transferred signal signals into an electrical voltage, and an output voltage is supplied to the gate of the second MIS transistor. This depletion type second MIS transistor causes the drain potential of the first MIS transistor to be changed in phase with the input electrical charges to reduce the gate-to-drain capacitance of the first MIS transistor to improve the charge-to-voltage conversion gain.Type: GrantFiled: April 2, 1990Date of Patent: July 2, 1991Assignee: Sony CorporaitonInventors: Tadakuni Narabu, Masaharu Hamasaki, Tetsuya Iizuka