Abstract: A synchronous differential logic system is provided for implementation of pipelined computational structures capable of hyperfrequency operation. An individual logic circuit has a differential cascode switch and a synchronous sense amplifier which operates as a latch. A plurality of differential inputs are connected to the differential cascode switch which produces complementary signals at first and second nodes. The cascode switch is connected to the synchronous sense latch which provides complementary output signals of the logic circuit. The synchronous sense latch comprises an equalization transistor and two cross-coupled inverters, each connected to first and second power supply buses. The equalization transistor is connected to the first and second outputs, of the logic gate and to a global system clock.