Patents Assigned to SPEEDATA LTD.
  • Patent number: 12613835
    Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.
    Type: Grant
    Filed: April 7, 2025
    Date of Patent: April 28, 2026
    Assignee: Speedata Ltd.
    Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
  • Patent number: 12468572
    Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.
    Type: Grant
    Filed: December 6, 2023
    Date of Patent: November 11, 2025
    Assignee: Speedata Ltd.
    Inventors: Yoav Etsion, Dani Voitsechov
  • Patent number: 12326860
    Abstract: An apparatus for applying database commands to one or more database tables includes a memory and a hardware-implemented pipeline. The hardware-implemented pipeline includes one or more table-processing circuits, and is configured to receive a stream of input records drawn from the one or more database tables, to parse first records, from among the input records, into a key and one or more fields other than the key, to store at least parts of the first records in the memory so as to be accessible using the key, and to apply a database command by matching at least parts of second records from among the input records to the at least parts of the first records stored in the memory, in accordance with the key.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: June 10, 2025
    Assignee: Speedata Ltd.
    Inventors: Rafi Shalom, Kobby Carmona
  • Patent number: 12298939
    Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: May 13, 2025
    Assignee: Speedata Ltd.
    Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
  • Patent number: 12038922
    Abstract: An apparatus for applying database commands to one or more database tables includes a memory and a hardware-implemented pipeline. The hardware-implemented pipeline includes one or more table-processing circuits, and is configured to receive a stream of input records drawn from the one or more database tables, to parse first records, from among the input records, into a key and one or more fields other than the key, to store at least parts of the first records in the memory so as to be accessible using the key, and to apply a database command by matching at least parts of second records from among the input records to the at least parts of the first records stored in the memory, in accordance with the key.
    Type: Grant
    Filed: October 17, 2021
    Date of Patent: July 16, 2024
    Assignee: SPEEDATA LTD.
    Inventors: Rafi Shalom, Kobby Carmona
  • Patent number: 11900156
    Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 13, 2024
    Assignee: SPEEDATA LTD.
    Inventors: Yoav Etsion, Dani Voitsechov
  • Patent number: 11874800
    Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: January 16, 2024
    Assignee: SPEEDATA LTD.
    Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
  • Patent number: 11586587
    Abstract: A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: February 21, 2023
    Assignee: SPEEDATA LTD.
    Inventors: Dani Voitsechov, Yoav Etsion, Rafi Shalom
  • Patent number: 11354157
    Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive a software program represented as a set of interconnected Data-Flow Graphs (DFGs), each DFG specifying code instructions that perform a respective portion of the software program, to schedule execution of the DFGs in time alternation, and, for each DFG being scheduled, to configure at least some of the compute nodes and interconnects in the compute fabric to execute the code instructions specified in the DFG, and send to the compute fabric multiple threads that each executes the code instructions specified in the DFG.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: June 7, 2022
    Assignee: SPEEDATA LTD.
    Inventors: Dani Voitsechov, Yoav Etsion
  • Patent number: 11175922
    Abstract: A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 16, 2021
    Assignee: SPEEDATA LTD.
    Inventors: Yoav Etsion, Dani Voitsechov, Evgeni Krimer, Jonathan Friedmann
  • Patent number: 11003458
    Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 11, 2021
    Assignee: SPEEDATA LTD.
    Inventors: Yoav Etsion, Dani Voitsechov