Abstract: A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.

Abstract: A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.

Abstract: A system and method for computational unification of heterogeneous implicit and explicit processing elements which supports the aggregation of any number of such processing elements. The system and method of the present invention supports the generation of a unified executable program through the use of directive statements which are analyzed in conjunction with the semantic structures in the parsed source code to generate appropriate source code targeted to the implicit and explicit processing elements. The computational unification system and method of the present invention further embodies expertise with the particular programming style and idiom of the various processing elements.

Abstract: A system and method for fair dynamic priority conflict resolution in a multi-processor computer system having shared resources wherein each multi-processor seeking access to said shared resource possesses a common priority level. In the occurrence of a priority tie or when a single port is active, a typical dynamic conflict resolution scheme is altered to ensure fair resolution of the conflict or tie. Upon determination that a priority conflict tie exists, one of the processor elements is selected based on a predetermined priority level. The identity of the selected processor element and the configuration of the conflict priority tie is stored. Upon a subsequent conflict priority tie having the same configuration as a previous priority conflict tie, the processor elements selected in previous ties are prevented from being selected in subsequent priority conflict ties until all of the processor elements in a particular priority tie configuration have been selected.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Abstract: A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Abstract: An enhanced switch/network adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain.

Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.

Abstract: A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elements and reconfigurable devices with course grained logic elements or a reconfigurable processor comprising both reconfigurable devices with fine grained elements and non-reconfigurable devices with course grained elements.

Abstract: A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips.

Abstract: A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.

Abstract: An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it.

Abstract: An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Abstract: A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (“MAP”) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (“FPGAs”) which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory (“ROM”) located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Abstract: A system and method for fair dynamic priority conflict resolution in a multi-processor computer system having shared resources wherein each multi-processor seeking access to said shared resource possesses a common priority level. In the occurrence of a priority tie or when a single port is active, a typical dynamic conflict resolution scheme is altered to ensure fair resolution of the conflict or tie. Upon determination that a priority conflict tie exists, one of the processor elements is selected based on a predetermined priority level. The identity of the selected processor element and the configuration of the conflict priority tie is stored. Upon a subsequent conflict priority tie having the same configuration as a previous priority conflict tie, the processor elements selected in previous ties are prevented from being selected in subsequent priority conflict ties until all of the processor elements in a particular priority tie configuration have been selected.

Abstract: A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.