Abstract: A method and circuit for detecting primary switch (12) status in isolated DC/DC converters by observing the falling speed of the voltage level at the sensing point (node Z) is disclosed. It is noted that high impedance oscillation has a relatively slow falling or rising time when compared to a valid signal. By observing the falling or rising time of a given signal during the appropriate time period, a determination can be made to differentiate a valid signal and an oscillating signal. More specifically, two reference voltages (A & B) are provided to compare against node Z voltage to generate a sense pulse. A reference pulse having a predefined duration is compared to the sense pulse. If the duration of the sense pulse is greater than the duration of the reference pulse, a latch is used to generate a low output signal. If the duration of the sense pulse is less than the duration of the reference pulse, a high output signal is generated.

Abstract: Circuits and methods are provided for operating a transistor as rectifier based upon the detected Vds of the transistor. In sensing the Vds voltage of the SRMOS, during positive conduction, the SRMOS body diode will conduct and the Vds of the SRMOS becomes that of a forward body diode voltage, which may, depending on the type of the device, be approximately -0.6V. If this voltage level is sensed, it may indicates that the SRMOS is turned off too early. During reverse conduction, Vds is non-existent (which is similar to a diode). In this case, the SRMOS may be turned off too late. Thus, by examining Vds, the SRMOS can be operated in such a manner so that it is turned off at an optimal point in time.