Abstract: A conversion between two texture compression formats comprises calculations performed at index-level for reducing handling of values with color bit-length and an amount of calculations with color values. Format conversion can thus be performed in real time upon displaying an image using the compressed texture data, without significant slowing down of a display rate of the images. It may be implemented in particular for conversion from DXT1—to ETC1 compression format, and a non-flipped or flipped orientation of an ETC1—compressed texture data block can thus be determined from said texture data block as initially compressed in DXT1 format.

Abstract: The present invention relates to devices, methods, mobile communication terminals, computer programs and storage mediums for frequency control. The frequency control device for a mobile communication terminal only uses one crystal oscillator, but can access different access networks at the same time. The frequency control device may control the output of the crystal oscillator based on a plurality of frequency offset estimation results and the service performance of access network corresponding to the frequency offset estimation results. Therefore, the flexibility of frequency offset control may be improved and better service may be provided to users.

Abstract: A method of data transmission includes establishing a buffer for TCP/IP data packets, receiving and buffering the TCP/IP data packets including TCP payloads and TCP ACKs. A queue of the buffered TCP/IP data is adjusted in accordance with header information of the TCP/IP data packets. The buffered TCP/IP data packets are transmitted sequentially. The method significantly reduces the TCP ACKs, which are transmitted with priority, thereby reducing the round-trip time delay, and improving the data transmission efficiency. An apparatus configured to perform this method is also described.

Abstract: A method of determining a calibration of a near field communication, NFC, device, the NFC device comprising a receiver circuit, a transmitter circuit and a load modulator circuit, the method comprising: generating a carrier signal in the transmitter circuit, generating a modulation signal in the load modulator circuit, generating a modulated carrier signal, comprising first and second frequencies, by applying the modulation signal to the carrier signal, applying the modulated carrier signal at an input of the receiver circuit, and determining a response parameter of the receiver circuit on the basis of the response of the receiver circuit to the first and second frequencies in the modulated carrier signal.

Abstract: A signal is detected and an unwanted jamming signal is removed from the detected signal. Respective first, second and third correlations between a received signal and signals at first, second and third frequencies are determined over a plurality of taps. The second frequency is higher than the first frequency and lower than the third frequency, and is equally spaced from the first and third frequencies. The second frequency is adapted to a frequency of the received signal such that peaks in the first and third correlations after corresponding adaptation of the first and third frequencies have substantially equal magnitudes. A difference is determined between non-peak magnitudes of the first and third correlations; and at least one of the correlations is compensated for the effects of the jamming signal, based on said difference.

Abstract: The present invention provides a method for analyzing a digital image comprising a plurality of pixels representing a scene. The method comprising steps of obtaining pixel chromaticity information, providing, combinations each having a corresponding surface and a corresponding illuminant, performing a global scene surface-illuminant classification by determining hypothesis scores, accumulating hypothesis scores, thereby obtaining a global illuminant/surface statistic representing an estimate of a distribution of illuminants and/or surfaces in the scene as represented by the digital image. Other methods are also provided. Apparatuses for carrying out the methods are also provided.

Abstract: An emitter for modulating and emitting an orthogonal frequency division multiplexing signal through a transmission channel (TC), comprising a frequency-to-time converter for converting symbols to be transmitted into time symbols, and means for serializing and amplifying said time symbol so as to emit it as an OFDM signal through said transmission channel, said emitter further comprising: means (12) for clipping said time symbols; time-to-frequency convertor (13) for converting said time symbols; and means for applying a set of data subcarriers of the outputs of said time-to-frequency converter as inputs of said frequency-to-time converter wherein out-of-band subcarriers are set to zero and the clipping level is set to a minimum level allowing the amplifier to operate in an efficient region.

Abstract: It is proposed a method for controlling the transmission of a sampled voice signal over a Bluetooth® radio link. The method comprises the steps of: a) monitoring the sampled voice signal for detecting whether the sampled voice signal comprises a number of consecutive silence samples; and b) halting the transmission of the sampled voice signal over the Bluetooth® radio link after having transmitted said consecutive silence samples.

Abstract: Electronic device (101) comprising a power source (110), a power management unit (102) coupled to the power source, and a set of loads (103a,103b, 103c,103d), the power management unit comprising a set of voltage regulators blocks (104a,104b, 104c,104d), each voltage regulator block being respectively coupled to an associated load of the set of loads for allowing power transfer from the power source to the load. The electronic device comprises a spike detector block (106), coupled to each of the voltage regulator blocks, and configured to detect a spike in a voltage signal from a voltage regulator block for testing the presence and the operability of a decoupling capacitor (Ca, Cb, Cc, Cd) between an output of the voltage regulator block and an input of the associated load.

Abstract: It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and—each line has an termination (Z1, Z2) on both the first and second ends of the line by connecting a first impedance (Z1) to the first end of the line and a second impedance (Z2) to the second end of the line.

Abstract: Methods of processing a frame in a video sequence of digital images are provided. The methods include determining a global motion vector for the frame relative to a previous frame in the sequence, deriving a jitter function from the global motion vector, the jitter function including an estimate of undesired motion of the frame relative to the previous frame, and determining whether the frame is blurred above a first predetermined threshold. If the frame is blurred above the first predetermined threshold, stabilizing the frame using the jitter function and applying a deblur function to the frame.

Abstract: A voltage converter device converts an input signal having a given input voltage value into an output signal having an output voltage different from the input voltage. The device comprises a main module, arranged between an input terminal and a first circuit node, The device is adapted to output at the first circuit node a pulse-width-modulated signal switching between a first voltage value and a second voltage value, defining a switching range, by switching successively between a first mode of operation and a second mode of operation. The switching range of the pulse width modulation has an amplitude, calculated as the absolute difference between the first and the second voltage value, inferior or equal to half the input voltage.

Abstract: It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: monitoring (S100) a value of a parameter of the core, the parameter being a critical parameter for a safe operating of the core; determining whether the monitored value reaches a trigger value; when the monitored value reaches the trigger value (S120): modifying the clock rate of the core (S130) by decreasing the ratio of active cycles of the clock; and running the core at the clock rate modified (S140) by decreasing the ratio of active cycles of the clock; when the monitored value reaches a second time the trigger value (S170): modifying the clock rate of the core (S180) by increasing the ratio of active cycles of the clock; and running the core at the clock rate (S190) modified by increasing the ratio of active cycles of the clock.

Abstract: A digital class D amplifier (10) is disclosed, comprising a pulse width modulator (PW Mod) comprising: a digital loop filter (Loop F) adapted to receive an input signal (x[n]) and a feedback signal (fb[n]), the digital loop filter (Loop_F) being adapted to process at a clock frequency (f_s) said input and feedback signals for providing as output a filtered digital signal (w[n]); a PWM conversion module (PW_CM) having an input (24) for receiving the filtered digital signal (w[n]) and having a first output (25) connected to the digital loop filter (Loop F), the PWM conversion module being adapted for processing the filtered digital signal (w[n]) and providing at said first output (25) the feedback signal (fb[n]).

Abstract: A mobile telephony radiocommunication management process, with first time slots and second time slots being provided independently of each other, said process comprising the default selection of first time slots for transmitting/receiving first bursts corresponding to these first time slots, and in the case of a first time slot at least partially overlapping with a second time slot, choosing the first time slot or the second time slot, for respectively transmitting/receiving the first burst corresponding to the first time slot or receiving the second burst corresponding to the second time slot, with this choice being made so as to minimize the number of second bursts received for a given result.

Abstract: A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.

Abstract: Described herein are methods and systems for performing functions associated with a non-functional key of a keyboard present on electronic devices such as cell-phones, telephones, ATMs, etc. The electronic device is operated in a non-functional key (NFK) coding mode using NFK codes (108) that are provided to a memory component (202) of the electronic device (102). In the NFK coding mode, a user is allowed to enter functional keys in a coded sequence. Based on the NFK codes (108), the coded sequence is used to identify a function associated with a non-functional key of the keyboard and the identified function is indicated to a processor (204) of the electronic device (102) for execution.

Abstract: High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Abstract: A multiphase buck converter (10) is disclosed, comprising: —a first buck converter branch (SD1, L1) comprising a first core section (COR1), a first power section (PWR1) having a first output node (LX1), a first coil (11) having a first end connected to the first output node (LX1), the first power section (PWR1) being adapted to be controlled by the first core section (COR1) for providing to the coil (L1) a coil current (I1), the first core section (COR1) and the first power section (PWR1) being integrated in a chip (IC); —a second buck converter branch (SD2, L2) comprising a second core section (COR2), a second power section (PWR2) having a second output node (LX2), a second coil (L2) having a first end connected to the second output node (LX2), the second power section (PWR2) being adapted to be controlled by the second core section (COR2) for providing to the second coil (L2) a second coil current (I2), the second core section (COR2) and the second power section (PWR2) being integrated in said chip (IC); —a

Abstract: A method of self-test for a near-field communication (NFC) radio frequency (RF) front-end unit comprising one antenna driver and at least one unit from a group comprising one reader and one card emulator, the RF front-end unit being connected to a digital front-end unit, wherein the antenna driver and the unit are interconnected through a first connection line via their respective first input-output interface and are also interconnected through a second connection line via their respective second input-output interface, the digital front-end unit being connected to the second connection line, the method comprising: activating the antenna driver and the unit based on control signals; —generating a first signal onto the first connection line by modulating a respective first bitstream; —retrieving a second bitstream from the second connection line, by demodulating the first signal; and, —determining an outcome of the self-test by monitoring the demodulated signal.