Abstract: A microelectromechanical device having a mobile structure including mobile arms formed from a composite material and having a fixed structure including fixed arms capacitively coupled to the mobile arms. The composite material includes core regions of insulating material and a silicon coating.

Abstract: A pressure sensor is for positioning within a structure. The pressure sensor may include a pressure sensor integrated circuit (IC) having a pressure sensor circuit responsive to bending, and a transceiver circuit coupled to the pressure sensor circuit. The pressure sensor may include a support body having a recess therein coupled to the pressure sensor IC so that the pressure sensor IC bends into the recess when the pressure sensor IC is subjected to external pressure.

Abstract: An embodiment of a simulation tool includes a path determiner and a simulator. The path determiner is configured to identify a first communication path between first and second devices of a system, and the simulator is configured to simulate a routing of a first item from one of the first and second devices to the other of the first and second devices via the identified path. The path determiner may also be configured to identify the communication path before the simulator simulates the routing of the item, or to identify the communication path while the simulator is inactive.

Abstract: The integrated electronic device is for detecting a local parameter related to a force experienced in a predetermined direction within a solid structure. The device includes a semiconductor substrate having a substantially planar region that defines a plane substantially perpendicular to the predetermined direction. At least one sensor detects the local parameter at least in the predetermined direction with a piezo-resistive effect. At least one substantially planar face is arranged in a portion of the integrated electronic device, the face belonging to a inclined plane by a predetermined angle relative to the plane perpendicular to the predetermined direction, which plane is defined by the substantially planar region of the substrate. The predetermined angle is defined such as to reduce forces acting in directions other than the predetermined direction at the portion of the device around the at least one sensor.

Abstract: The method is for protecting the digital contents of a solid state memory including a microprocessor. A microprocessor inserts at least an interruption during a copy or a reading of the digital contents and proceeds with the copy or reading only subsequently to a verification of a PIN. In particular, the verification provides control that the PIN is inserted manually. Also, a solid state memory includes a microprocessor programmed for inserting at least an interruption in a copy or reading of digital contents of the memory, for verifying a PIN, and for proceeding with the copy or the reading, if the PIN is inserted correctly.

Abstract: Both a chalcogenide select device and a chalcogenide memory element are formed within vias within dielectrics. As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material is formed within the same via with the memory element. In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer; in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide used to form a memory element and the lance material is achieved by providing a pin hole opening in a dielectric, which separates the chalcogenide and the lance material.

Abstract: A microfluidic device for nucleic acid analysis includes a monolithic semiconductor body (13), a microfluidic circuit (10), at least partially accommodated in the monolithic semiconductor body (13), and a micropump (11). The microfluidic circuit (10) includes a sample preparation channel (18) formed on the monolithic semiconductor body (13) and at least one microfluidic channel (20, 22) buried in the monolithic semiconductor body (13). The micropump (11), includes a plurality of sealed chambers (40) provided with respective openable sealing elements (41) and having a first pressure therein that is different from a second pressure in the microfluidic circuit (10). In addition, the micropump (11) and the microfluidic circuit (10) are configured so that opening the openable sealing elements (41) provides fluidic coupling between the respective chambers (40) and the microfluidic circuit (10). The openable sealing elements (41) are integrated in the monolithic semiconductor body (13).

Abstract: A bifunctional compound comprising a molecular unit (I) intercalating between nucleobases (B) of nucleic acids, an active molecular unit (AD) capable of emitting a detectable signal, and optionally a spacer unit, in which the active molecular unit (AD) is selected from amongst chemical entities having a structure such as to interact electronically with the intercalating molecular unit (I) in such a way that, during the reaction of oxidation, the reduction-oxidation potential (EI+/I) of the semicouple I+/I defined by the intercalating molecular unit (I) is lower than the reduction-oxidation potential (EB+/B) of the semicouple B+/B defined by the nucleobases (B), and in such a way that, during the reaction of reduction, the reduction-oxidation potential (EI/I?) of the semicouple I/I? defined by the intercalating molecular unit (I) is higher than the reduction-oxidation potential (EB/B?) of the semicouple B/B? defined by the nucleobases (B).

Abstract: A plurality of planar electrodes (5) in a microchannel (4) is used for separation, lysis and PCR in a chip (10). Cells from a sample are brought to the electrodes (5). Depending on sample properties, phase pattern, frequency and voltage of the electrodes and flow velocity are chosen to trap target cells (16) using DEP, whereas the majority of unwanted cells (17) flushes through. After separation the target cell (16) are lysed while still trapped. Lysis is carried out by applying RF pulses and/or thermally so as to change the dielectric properties of the trapped cells. After lysis, the target cells (16) are amplified within the microchannel (4), so as to obtain separation, lysis and PCR on same chip (1).

Abstract: In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([a0a1 . . . aN?1])=??i(?1)ai where the symbols ai belong to the set {0, 1} and the sum extends for values of i from 0 to N?1. An encoder is configured to satisfy at least one of the following characteristics: a) blocks of symbols with a given length (L) are used for encoding, wherein RDS=RDS0+4.K, where K is an integer, RDS is the said running digital sum, RDS0 is defined as zero for even values of the said length (L), and one for odd values of said length (L), and b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks.

Abstract: A system provides two distinct solutions for encoding and decoding servo positioning data for a hard disk drive. A first solution includes: encoding each group of four bits of a pattern signal in a Matched Spectral Null (MSN) format through an intermediate rate 4/6 code; providing a duplicated bit for each bit of the six bit code word obtained with the previous step. A second solution includes: encoding each group of four bit of the pattern signal adding a parity check bit as an intermediate rate ? code; encoding each of the five bits using the biphase map. Both solutions include subsequently: reading a servo wedge information signal using a read and write channel of the hard disk drive; and using a trellis Partial Response decoding scheme matched to the encoded word for obtaining angular and radial information for the head positioning.

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

Abstract: A high-precision biasing circuit is provided for a CMOS cascode stage with inductive load and degeneration. The cascode stage includes at least two MOS transistors serially connected between a first voltage reference and a second voltage reference. The biasing circuit includes at least a first MOS replica transistor and a second MOS replica transistor, and two current generators for biasing the first and second MOS replica transistors. A circuit block detects a voltage value on a terminal of the second replica MOS transistor and applies a voltage to a gate terminal of the first replica transistor. Two circuit block implementations include a voltage amplifier and a folded cascode amplifier closed in a shunt feedback. Both implementations allow the threshold voltages of the cascode stage transistors to be tracked, as well as their Early and body effects.

Abstract: An integrated circuit includes a first access pin and a second access pin, and an electronic circuit for trimming a portion of the integrated circuit. The electronic circuit includes a memory element, and a regulation circuit for modifying the memory element. The regulation circuit includes an error amplifier for comparing an output voltage of the portion of the integrated circuit to be trimmed with an internal voltage reference. A comparator includes a first input connected to an output of the error amplifier and to the first access pin. A first switch is connected between the output of the error amplifier and the first input of the comparator. A second comparator includes a first input connected to the second access pin, and an output connected to the first switch for control thereof. A second switch is connected to the output of the error amplifier and to the first access pin.

Abstract: A class D amplifier includes an input integrating stage and a modulating stage for modulating the integrated input signal output by the integrating stage. The modulating stage uses as a carrier an alternate waveform of a frequency sufficiently higher than the frequency band of the analog input signal. The modulating stage further outputs a digital signal switching between a positive voltage and a negative voltage, and whose average value represents an amplified replica of the input analog signal. The class D amplifier further includes an output power stage producing an output digital signal. A feedback line including a resistor is connected between the output of the output power stage and an input node of an operational amplifier. The class D amplifier also includes a low-pass filter reconstructing an output analog signal, and a delay stage.

Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract: A circuit generates a regulated voltage, in particular for gate terminals of non-volatile memory cells of the floating gate type. The circuit includes a generator circuit adapted to generate an unregulated voltage on its output. A comparator circuit is coupled to the output of the generator circuit including a reference element including a non-volatile memory cell of the floating gate type and adapted to output an error signal tied to the difference between the unregulated voltage and the threshold voltage of the cell. A regulator circuit is coupled to the output of the comparator circuit and is operative to regulate the unregulated voltage based on the value of the error signal. The regulated voltage is made programmable and tied to the parameters of the memory cell.