Abstract: A circuit module includes a printed circuit board (PCB) having a first side, a second side, and a bottom perimeter edge. The PCB exhibits a first thickness along the bottom perimeter edge. The first side includes a recessed area and, in that recessed area, the PCB has a second thickness that is less than the first thickness. A plurality of integrated circuits (ICs) are fixed to the PCB in the recessed area. A plurality of module contacts are connected to the ICs and are disposed along at least one of the first and second sides and are configured to provide electrical connection between the circuit module and an edge connector.

Abstract: Flexible circuitry is populated with integrated circuitry (ICs), and contacts are distributed along the flexible circuitry to provide connection to an application environment. The flexible circuitry is disposed about a rigid substrate, placing the ICs on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate is preferably devised from thermally-conductive materials and one or more thermal spreaders are in thermal contact with at least some of the ICs. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

Abstract: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices. In preferred embodiments, the plastic body of one or more leaded packaged ICs bear conductive traces that create circuitry to provide stacking related electrical interconnections between the constituent ICs of a stacked module without the use of separate interposers or carrier structures. Typically, the circuitry is borne by the body of the upper one of the ICs of a two-IC leaded package stack to implement stacking-related connections between the constituent ICs.

Abstract: A managed memory system is provided. More specifically, in one embodiment, there is provided a system including a memory device and a switch coupled to the memory device. The switch has at least a first switch position and a second switch position. The system also includes a memory controller coupled to the first switch position and a processor interface coupled to the second switch position.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.

Abstract: The present invention provides a system and method for devising stackable assemblies that may be then stacked to create a stacked circuit module. One or more integrated circuit (IC) die are disposed on one or more sides of a redistribution substrate that is preferably flexible circuitry. In some preferred embodiments, the die and redistribution substrate are bonded together and wire-bond connected. Two or more stackable assemblies are interconnected through frame members to create low profile high density stacked circuit modules.

Abstract: A system a method for assembling dual-die integrated circuit packages using thermocompression bonding or thermosonic bonding to bond a second die to a substrate opposite a first die bonded to the substrate. The second die is bonded using heat conducted through the first die to the substrate, and optionally through an underfill material. The first and second die are connected such that bumps are connected to common bonding pads on the substrate. Bumps on one of the die extend through openings in the substrate to connect to the common bonding pads. The bonding pads are within the perimeter of the first die.

Abstract: Two or more integrated circuits are stacked into a high density circuit module. The lower IC is inverted. Electrical connection to the integrated circuits is made by module contacts on a flexible circuit extending along the lower portion of the module. In one embodiment, the flexible circuit provides a balanced electrical connection to two CSP integrated circuits. In another embodiment, the flexible circuit provides a balanced electrical connection to inter-flex contacts of additional flexible circuits on two submodules. The additional flexible circuits provide further balanced connections to CSP integrated circuits in each submodule.

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.

Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.

Abstract: Multiple DIMM circuits or ins tantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.

Abstract: A combination composed from a form standard and a CSP is attached to flex circuitry. Solder paste is applied to first selected locations on the flex circuitry and adhesive is applied to second selected locations on the flex circuitry. The flex circuitry and the combination of the form standard and CSP are brought into proximity with each other. During solder reflow operation, a force is applied that tends to bring the combination and flex circuitry closer together. As the heat of solder reflow melts the contacts of the CSP, the combination collapses toward the flex circuitry displacing the adhesive as the solder paste and contacts merge into solder joints. In a preferred embodiment, the form standard will be devised of heat transference material, a metal, for example, such as copper would be preferred, to improve thermal performance. In other embodiments, the methods of the invention may be used to attach a CSP without a form standard to flex circuitry.

Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.

Abstract: The present invention provides methods for constructing stacked circuit modules and precursor assemblies with flexible circuitry. Using the methods of the present invention, a single set of flexible circuitry whether articulated as one or two flex circuits may be employed with CSP devices of a variety of configurations either with or without form standards.

Abstract: Two or more integrated circuits are stacked into a high density circuit module. The lower IC is inverted. Electrical connection to the integrated circuits is made by module contacts on a flexible circuit extending along the lower portion of the module. In one embodiment, the flexible circuit provides a balanced electrical connection to two CSP integrated circuits. In another embodiment, the flexible circuit provides a balanced electrical connection to inter-flex contacts of additional flexible circuits on two submodules. The additional flexible circuits provide further balanced connections to CSP integrated circuits in each submodule.

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract: There is provided a stacked IC module including first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages, and a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.

Abstract: A system and method for electrically and thermally coupling adjacent IC packages to one another in a stacked configuration is provided. A flex circuit is inserted in part between ICs to be stacked and provides a connective field that provides plural contact areas that connect to respective leads of the ICs. Thus, the flex does not require discrete leads which must be individually aligned with the individual leads of the constituent ICs employed in the stack. The principle may be employed to aggregate two or more contact areas for respective connection to leads of constituent ICs but is most profitably employed with a continuous connective field that provides contact areas for many leads of the ICs.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.